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nb/intel/i945: Enable and allocate 8M for TSEG 

TSEG can be used as a stage cache and SMM can be relocated here.

Tested on Intel D945GCLF, still boots.

Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25592
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-04-09 22:03:21 +02:00 committed by Patrick Georgi
parent a16cffe480
commit e07df9d783
1 changed files with 5 additions and 0 deletions
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5
src/northbridge/intel/i945/early_init.c
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@ -192,6 +192,11 @@ static void i945_setup_bars(void)
gfxsize = 2;
pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);