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vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3313 

Update FSP headers for Tiger Lake platform generated based FSP
version 3313. Previous version was 3274.
Changes Include:
1. Update comments
2. Fix comment typos
3. UPD offset updates

BUG=b:163582213
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2784c5b7c8f71c1355c1c36a27cc88080c7c2647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Srinidhi N Kaushik 2020-08-11 13:40:16 -07:00 committed by Nick Vaccaro
parent 90883287b5
commit e0836b0fcb
2 changed files with 345 additions and 344 deletions
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16
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
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@ -251,7 +251,7 @@ typedef struct {
UINT8 Reserved1[3]; UINT8 Reserved1[3];
/** Offset 0x0130 - Intel Enhanced Debug /** Offset 0x0130 - Intel Enhanced Debug
DEPRECATED <b>@deprecated</b> - Not used and has no effect
0 : Disable, 0x400000 : Enable 0 : Disable, 0x400000 : Enable
**/ **/
UINT32 IedSize; UINT32 IedSize;
@ -310,8 +310,8 @@ typedef struct {
**/ **/
UINT8 DciDbcMode; UINT8 DciDbcMode;
/** Offset 0x014F - Enable DCI ModPHY Pwoer Gate /** Offset 0x014F - Enable DCI ModPHY Power Gate
Enable ModPHY Pwoer Gate when DCI is enabled Enable ModPHY Power Gate when DCI is enabled
$EN_DIS $EN_DIS
**/ **/
UINT8 DciModphyPg; UINT8 DciModphyPg;
@ -797,7 +797,7 @@ typedef struct {
**/ **/
UINT8 RealtimeMemoryTiming; UINT8 RealtimeMemoryTiming;
/** Offset 0x025A - This is policy to control iTBT PCIe Multiple Segment setting. /** Offset 0x025A - iTBT PCIe Multiple Segment setting
When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable. TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable.
$EN_DIS $EN_DIS
@ -1468,7 +1468,7 @@ typedef struct {
**/ **/
UINT8 PchSataHsioTxGen3DeEmph[8]; UINT8 PchSataHsioTxGen3DeEmph[8];
/** Offset 0x056F - PCH LPC Enhance the port 8xh decoding /** Offset 0x056F - PCH LPC Enhanced Port 80 Decoding
Original LPC only decodes one byte of port 80h. Original LPC only decodes one byte of port 80h.
$EN_DIS $EN_DIS
**/ **/
@ -1476,7 +1476,7 @@ typedef struct {
/** Offset 0x0570 - PCH Port80 Route /** Offset 0x0570 - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
$EN_DIS 0:LPC, 1:PCI
**/ **/
UINT8 PchPort80Route; UINT8 PchPort80Route;
@ -2036,7 +2036,7 @@ typedef struct {
UINT16 ChHashMask; UINT16 ChHashMask;
/** Offset 0x0630 - Base reference clock value /** Offset 0x0630 - Base reference clock value
Base reference clock value, in Hertz(Default is 125Hz) Base reference clock value, in Hertz(Default is 100Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/ **/
UINT32 BClkFrequency; UINT32 BClkFrequency;
@ -2508,7 +2508,7 @@ typedef struct {
/** Offset 0x0920 /** Offset 0x0920
**/ **/
UINT8 UnusedUpdSpace25[6]; UINT8 UnusedUpdSpace26[6];
/** Offset 0x0926 /** Offset 0x0926
**/ **/

673
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
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