From e0849350aa74c58751675da389d717a93c365030 Mon Sep 17 00:00:00 2001 From: zbao Date: Tue, 24 May 2016 21:21:26 +0800 Subject: [PATCH] AMD/spi: Do not reset fifo after skipping the sent bytes After we skip the bytes we send, the fifo pointer is at right position. Reseting the fifo will change it to a wrong place. Please view the flashrom code, which tells the same thing. https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257 Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/14955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/southbridge/amd/agesa/hudson/spi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index e8ab372eaa..31160bdcd9 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -143,7 +143,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, cmd = spi_read(SPI_REG_FIFO); } - reset_internal_fifo_pointer(); for (count = 0; count < bytesin; count++, din++) { *(uint8_t *)din = spi_read(SPI_REG_FIFO); }