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device,drivers/: Drop some __SIMPLE_DEVICE__ use 

The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.

Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2019-09-26 22:33:51 +03:00 committed by Patrick Georgi
parent 1463a2a04d
commit e088721f71
3 changed files with 7 additions and 15 deletions
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8
src/commonlib/storage/pci_sdhci.c
View File

@ -12,10 +12,6 @@
* GNU General Public License for more details.
*/
#if ENV_RAMSTAGE
#define __SIMPLE_DEVICE__ 1
#endif
#include <arch/early_variables.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
@ -54,11 +50,11 @@ struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr)
return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr);
}
struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev)
struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
{
uint32_t addr;
addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
if (addr == ((uint32_t)~0)) {
sdhc_error("Error: PCI SDHCI not found\n");
return NULL;

2
src/device/pci_ops.c
View File

@ -11,8 +11,6 @@
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <console/console.h>
#include <device/pci.h>

12
src/drivers/uart/oxpcie_early.c
View File

@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <stddef.h>
#include <device/pci_ops.h>
@ -31,7 +29,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
{
pci_devfn_t device = PCI_DEV(bus, dev, 0);
u32 id = pci_read_config32(device, PCI_VENDOR_ID);
u32 id = pci_s_read_config32(device, PCI_VENDOR_ID);
switch (id) {
case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
/* On this device function 0 is the parallel port, and
@ -39,7 +37,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
* the UART.
*/
device = PCI_DEV(bus, dev, 3);
id = pci_read_config32(device, PCI_VENDOR_ID);
id = pci_s_read_config32(device, PCI_VENDOR_ID);
if (id != 0xc11b1415)
return -1;
break;
@ -56,12 +54,12 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
return -1;
/* Setup base address on device */
pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable memory on device */
u16 reg16 = pci_read_config16(device, PCI_COMMAND);
u16 reg16 = pci_s_read_config16(device, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(device, PCI_COMMAND, reg16);
pci_s_write_config16(device, PCI_COMMAND, reg16);
car_set_var(oxpcie_present, 1);
return 0;