northbridge/intel/i440bx: Registered SDRAM modules support and fixes
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Keith Hui
Stefan Reinauer
parent
6de1ee4a30
commit
e089a3f68d
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@ -258,7 +258,7 @@ static const u8 register_values[] = {
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* 01 4 KB
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* 10 8 KB
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* 11 Reserved
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*
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*
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* RPS bits Corresponding DRB register
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* [01:00] DRB[0], row 0
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* [03:02] DRB[1], row 1
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@ -721,19 +721,23 @@ static struct dimm_size spd_get_dimm_size(unsigned int device)
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*/
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static void set_dram_row_attributes(void)
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{
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int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc;
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int i, dra, drb, col, width, value, rps;
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u8 bpr; /* Top 8 bits of PGPOL */
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u8 nbxecc = 0; /* NBXCFG[31:24] */
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u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */
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edosd = 0;
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edo = 0;
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sd = 0;
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regsd = 1;
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rps = 0;
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drb = 0;
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bpr = 0;
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nbxecc = 0xff;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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unsigned int device;
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device = DIMM0 + i;
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bpr >>= 2;
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nbxecc >>= 2;
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/* First check if a DIMM is actually present. */
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value = spd_read_byte(device, SPD_MEMORY_TYPE);
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@ -742,13 +746,13 @@ static void set_dram_row_attributes(void)
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|| value == SPD_MEMORY_TYPE_SDRAM) {
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if (value == SPD_MEMORY_TYPE_EDO) {
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edosd |= 0x02;
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edo = 1;
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} else if (value == SPD_MEMORY_TYPE_SDRAM) {
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edosd |= 0x04;
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sd = 1;
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}
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PRINT_DEBUG("Found DIMM in slot %d\n", i);
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if (edosd == 0x06) {
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if (edo && sd) {
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print_err("Mixing EDO/SDRAM unsupported!\n");
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die("HALT\n");
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}
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@ -764,24 +768,38 @@ static void set_dram_row_attributes(void)
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* TODO: Other register than NBXCFG also needs this
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* ECC information.
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*/
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ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
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value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
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/* Data width */
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width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
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/* Exclude error checking data width from page size calculations */
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if (ecc) {
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if (value) {
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value = spd_read_byte(device,
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SPD_ERROR_CHECKING_SDRAM_WIDTH);
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width -= value;
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/* ### ECC */
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/* Clear top 2 bits to help set up NBXCFG. */
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ecc &= 0x3f;
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nbxecc &= 0x3f;
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} else {
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/* Without ECC, top 2 bits should be 11. */
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ecc |= 0xc0;
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nbxecc |= 0xc0;
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}
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/* If any installed DIMM is *not* registered, this system cannot be
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* configured for registered SDRAM.
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* By registered, only the address and control lines need to be, which
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* we can tell by reading SPD byte 21, bit 1.
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*/
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value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
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PRINT_DEBUG("DIMM is ");
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if ((value & MODULE_REGISTERED) == 0) {
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regsd = 0;
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PRINT_DEBUG("not ");
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}
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PRINT_DEBUG("registered\n");
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/* Calculate page size in bits. */
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value = ((1 << col) * width);
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@ -801,7 +819,6 @@ static void set_dram_row_attributes(void)
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* Second bank of 1-bank DIMMs "doesn't have
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* ECC" - or anything.
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*/
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ecc |= 0x80;
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if (dra == 2) {
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dra = 0x0; /* 2KB */
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} else if (dra == 4) {
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@ -878,7 +895,6 @@ static void set_dram_row_attributes(void)
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/* If there's no DIMM in the slot, set dra to 0x00. */
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dra = 0x00;
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ecc = 0xc0;
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/* Still have to propagate DRB over. */
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drb &= 0xff;
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drb |= (drb << 8);
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@ -895,7 +911,6 @@ static void set_dram_row_attributes(void)
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drb >>= 8;
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rps |= (dra & 0x0f) << (i * 4);
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nbxecc = (nbxecc >> 2) | (ecc & 0xc0);
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}
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/* Set paging policy register. */
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@ -910,20 +925,19 @@ static void set_dram_row_attributes(void)
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pci_write_config8(NB, NBXCFG + 3, nbxecc);
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PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc);
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/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
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* TODO: Registered SDRAM support.
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*/
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edosd &= 0x07;
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if (edosd & 0x02) {
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edosd |= 0x00;
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} else if (edosd & 0x04) {
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edosd |= 0x08;
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}
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edosd &= 0x18;
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/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */
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/* i will be used to set DRAMC[4:3]. */
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if (regsd && sd) {
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i = 0x10; // Registered SDRAM
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} else if (sd) {
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i = 0x08; // SDRAM
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} else {
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i = 0; // EDO
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}
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/* edosd is now in the form needed for DRAMC[4:3]. */
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value = pci_read_config8(NB, DRAMC) & 0xe7;
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value |= edosd;
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value |= i;
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pci_write_config8(NB, DRAMC, value);
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PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value);
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}
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