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guybrush: Add Kconfig for PSP eSPI and port80 

Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for
cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect
PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus
errors on guybrush.

BUG=b:185514903, b:184356693
TEST=Boot guybrush, observe no port80 codes from PSP

Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rob Barnes 2021-04-15 17:21:19 -06:00 committed by Patrick Georgi
parent 03dfd19e6e
commit e09b681e6e
3 changed files with 22 additions and 3 deletions
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1
src/mainboard/google/guybrush/Kconfig
View File

@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select PSP_DISABLE_POSTCODES
select SOC_AMD_CEZANNE select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_COMMON_BLOCK_USE_ESPI

13
src/soc/amd/cezanne/Kconfig
View File

@ -279,6 +279,19 @@ config AMDFW_CONFIG_FILE
string string
default "src/soc/amd/cezanne/fw.cfg" default "src/soc/amd/cezanne/fw.cfg"
config PSP_DISABLE_POSTCODES
bool "Disable PSP post codes"
help
Disables the output of port80 post codes from PSP.
config PSP_POSTCODES_ON_ESPI
bool "Use eSPI bus for PSP post codes"
default y
depends on !PSP_DISABLE_POSTCODES
help
Select to send PSP port80 post codes on eSPI bus.
If not selected, PSP port80 codes will be sent on LPC bus.
config PSP_LOAD_MP2_FW config PSP_LOAD_MP2_FW
bool bool
default n default n

11
src/soc/amd/cezanne/Makefile.inc
View File

@ -80,6 +80,14 @@ CEZANNE_FWM_POSITION=$(call int-add, \
FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
PSP_SOFTFUSE_BITS += 7
endif
ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y)
PSP_SOFTFUSE_BITS += 15
endif
ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
# Enable secure debug unlock # Enable secure debug unlock
PSP_SOFTFUSE_BITS += 0 PSP_SOFTFUSE_BITS += 0
@ -122,9 +130,6 @@ APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}'
# type = 0xb - See #55758 (NDA) for bit definitions. # type = 0xb - See #55758 (NDA) for bit definitions.
PSP_SOFTFUSE_BITS += 28 6 PSP_SOFTFUSE_BITS += 28 6
#hardcode post code to eSPI
PSP_SOFTFUSE_BITS += 15
# Helper function to return a value with given bit set # Helper function to return a value with given bit set
set-bit=$(call int-shift-left, 1 $(call _toint,$1)) set-bit=$(call int-shift-left, 1 $(call _toint,$1))
PSP_SOFTFUSE=$(shell A=$(call int-add, \ PSP_SOFTFUSE=$(shell A=$(call int-add, \