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All these boards already had the CACHE_AS_RAM option in their individual 

configs. I just moved it the the CPU that they all use.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Warren Turkal 2010-09-27 21:18:26 +00:00 committed by Stefan Reinauer
parent 768d8ea098
commit e0afe735a0
14 changed files with 8 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/cpu/amd/model_lx/Kconfig
View File

@ -1,25 +1,27 @@
config CPU_AMD_LX
bool
if CPU_AMD_LX
config CPU_SPECIFIC_OPTIONS
def_bool y
select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
default 0xc8000
depends on CPU_AMD_LX
config DCACHE_RAM_SIZE
hex
default 0x8000
depends on CPU_AMD_LX
config GEODE_VSA
bool
default y
depends on CPU_AMD_LX
select PCI_OPTION_ROM_RUN_REALMODE
config GEODE_VSA_FILE
bool "Add a VSA image"
depends on CPU_AMD_LX
help
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.
@ -29,9 +31,9 @@ config GEODE_VSA_FILE
config VSA_FILENAME
string "AMD Geode LX VSA path and filename"
depends on GEODE_VSA_FILE && CPU_AMD_LX
depends on GEODE_VSA_FILE
default "gpl_vsa_lx_102.bin"
help
The path and filename of the file to use as VSA.
endif # CPU_AMD_LX

1
src/mainboard/amd/db800/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR

1
src/mainboard/amd/norwich/Kconfig
View File

@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR

1
src/mainboard/artecgroup/dbe61/Kconfig
View File

@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR

1
src/mainboard/digitallogic/msm800sev/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR

1
src/mainboard/iei/pcisa-lx-800-r10/Kconfig
View File

@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR

1
src/mainboard/lippert/hurricane-lx/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512

1
src/mainboard/lippert/literunner-lx/Kconfig
View File

@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512

1
src/mainboard/lippert/roadrunner-lx/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
# Standard chip is a 512 KB FWH. Replacing it with a 1 MB
# SST 49LF008A is possible.
select BOARD_ROMSIZE_KB_512

1
src/mainboard/lippert/spacerunner-lx/Kconfig
View File

@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512

1
src/mainboard/pcengines/alix1c/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR

1
src/mainboard/pcengines/alix2d/Kconfig
View File

@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR

1
src/mainboard/traverse/geos/Kconfig
View File

@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR

1
src/mainboard/winent/pl6064/Kconfig
View File

@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR