soc/amd/stoneyridge/acpi: clean up global NVS
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Felix Held
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6f42678460
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@ -14,25 +14,15 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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/* Miscellaneous */
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Offset (0x00),
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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SCDP, 8, // 0x29 - SD_CD GPIO portid
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SCDO, 8, // 0x2A - GPIO pad offset relative to the community
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TMPS, 8, // 0x2B - Temperature Sensor ID
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TLVL, 8, // 0x2C - Throttle Level Limit
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FLVL, 8, // 0x2D - Current FAN Level
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TCRT, 8, // 0x2E - Critical Threshold
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TPSV, 8, // 0x2F - Passive Threshold
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TMAX, 8, // 0x30 - CPU Tj_max
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Offset (0x34), // 0x34 - AOAC Device Enables
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LIDS, 8, // 0x01 - LID State
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PWRS, 8, // 0x02 - AC Power State
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CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
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PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
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GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
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TMPS, 8, // 0x17 - Temperature Sensor ID
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TCRT, 8, // 0x18 - Critical Threshold
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TPSV, 8, // 0x19 - Passive Threshold
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Offset (0x20), // 0x20 - AOAC Device Enables
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, 5,
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IC0E, 1, // I2C0, 5
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IC1E, 1, // I2C1, 6
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@ -51,11 +41,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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, 2,
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ESPI, 1, // ESPI, 27
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, 4,
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FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM
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FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM
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FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM
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FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM
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EH10, 32, // 0x44 - EHCI BAR
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FW00, 16, // 0x24 - xHCI FW ROM addr, boot RAM
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FW02, 16, // 0x26 - xHCI FW ROM addr, Instruction RAM
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FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM
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FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM
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EH10, 32, // 0x30 - EHCI BAR
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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@ -17,32 +17,22 @@
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struct __packed global_nvs {
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/* Miscellaneous */
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uint8_t pcnt; /* 0x00 - Processor Count */
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uint8_t ppcm; /* 0x01 - Max PPC State */
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uint8_t lids; /* 0x02 - LID State */
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uint8_t pwrs; /* 0x03 - AC Power State */
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uint8_t dpte; /* 0x04 - Enable DPTF */
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uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
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uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
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uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
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uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */
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uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */
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uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */
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uint8_t scdp; /* 0x29 - SD_CD GPIO portid */
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uint8_t scdo; /* 0x2A - GPIO pad relative offset */
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uint8_t tmps; /* 0x2B - Temperature Sensor ID */
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uint8_t tlvl; /* 0x2C - Throttle Level Limit */
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uint8_t flvl; /* 0x2D - Current FAN Level */
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uint8_t tcrt; /* 0x2E - Critical Threshold */
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uint8_t tpsv; /* 0x2F - Passive Threshold */
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uint8_t tmax; /* 0x30 - CPU Tj_max */
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uint8_t pad1[3];
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aoac_devs_t aoac; /* 0x34 - AOAC device enables */
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uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */
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uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */
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uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */
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uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */
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uint32_t eh10; /* 0x40 - EHCI BAR */
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uint8_t unused[184];
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uint8_t lids; /* 0x01 - LID State */
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uint8_t pwrs; /* 0x02 - AC Power State */
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uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
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uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
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uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */
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uint8_t tmps; /* 0x17 - Temperature Sensor ID */
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uint8_t tcrt; /* 0x18 - Critical Threshold */
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uint8_t tpsv; /* 0x19 - Passive Threshold */
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uint8_t pad1[6];
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aoac_devs_t aoac; /* 0x20 - AOAC device enables */
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uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */
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uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */
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uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */
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uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */
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uint32_t eh10; /* 0x30 - EHCI BAR */
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uint8_t unused[204];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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