mb/google/nightfury: Update DPTF parameters
Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning. BUG=b:149226871 BRANCH=firmware-hatch-12672.B TEST=built and verified FAN worked by DPTF active policy Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#define DPTF_CPU_PASSIVE 50
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#define DPTF_CPU_PASSIVE 90
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#define DPTF_CPU_CRITICAL 105
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger"
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#define DPTF_TSR0_PASSIVE 45
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#define DPTF_TSR0_PASSIVE 75
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#define DPTF_TSR0_CRITICAL 90
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#define DPTF_TSR0_TABLET_PASSIVE 32
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#define DPTF_TSR0_TABLET_CRITICAL 90
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V"
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#define DPTF_TSR1_PASSIVE 45
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#define DPTF_TSR1_PASSIVE 70
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#define DPTF_TSR1_CRITICAL 90
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#define DPTF_TSR1_TABLET_PASSIVE 32
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#define DPTF_TSR1_TABLET_CRITICAL 90
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#define DPTF_TSR1_ACTIVE_AC0 48
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#define DPTF_TSR1_ACTIVE_AC1 46
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#define DPTF_TSR1_ACTIVE_AC2 44
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#define DPTF_TSR1_ACTIVE_AC3 41
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA"
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#define DPTF_TSR2_PASSIVE 45
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#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - GT"
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#define DPTF_TSR2_PASSIVE 75
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#define DPTF_TSR2_CRITICAL 90
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#define DPTF_TSR2_TABLET_PASSIVE 32
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#define DPTF_TSR2_TABLET_CRITICAL 90
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#define DPTF_TSR3_SENSOR_ID 3
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#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT"
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#define DPTF_TSR3_PASSIVE 45
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#define DPTF_TSR3_CRITICAL 90
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#define DPTF_TSR3_TABLET_PASSIVE 32
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#define DPTF_TSR3_TABLET_CRITICAL 90
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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@ -42,6 +35,42 @@ Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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})
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/* DFPS: Fan Performance States */
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Name (DFPS, Package () {
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0, // Revision
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 5900, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5400, 180, 1800},
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Package () {70, 0xFFFFFFFF, 4900, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4500, 115, 1150},
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Package () {50, 0xFFFFFFFF, 4000, 90, 900},
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Package () {40, 0xFFFFFFFF, 3000, 55, 550},
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Package () {30, 0xFFFFFFFF, 2200, 30, 300},
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Package () {20, 0xFFFFFFFF, 1600, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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Name (DART, Package () {
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0, // Revision
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/*
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, AC7, AC8, AC9
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*/
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Package () {
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\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 70, 63, 54, 48, 44, 0, 0, 0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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}
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
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/* Charger Throttle Effect on Charger (TSR0) */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 },
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/* CPU Throttle Effect on IA (TSR2) */
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/* CPU Throttle Effect on GT (TSR2) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
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/* CPU Throttle Effect on GT (TSR3) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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