mb/google/dedede/variants/drawcia: add charger input current throttling

Add charger input current throttling for drawcia system

BUG=None
BRANCH=None
TEST=Built and tested on drawcia system

Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Sumeet R Pawnikar 2020-08-18 17:30:44 +05:30 committed by Patrick Georgi
parent bcab8b0a41
commit e0ca33ce86
1 changed files with 7 additions and 1 deletions

View File

@ -58,7 +58,7 @@ chip soc/intel/jasperlake
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)"
register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)"
register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 1000)"
register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)"
register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
@ -80,6 +80,12 @@ chip soc/intel/jasperlake
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000,}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf[0]" = "{ 255, 3000 }"
register "controls.charger_perf[1]" = "{ 24, 1500 }"
register "controls.charger_perf[2]" = "{ 16, 1000 }"
register "controls.charger_perf[3]" = "{ 8, 500 }"
device generic 0 on end
end
end # SA Thermal device