From e0d497a3b639c32cb6d8d8dba7d2e8f98739a02e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 6 Dec 2022 23:56:29 +0530
Subject: [PATCH] mb/google/rex: Enable S0ix

This patch enables S0ix for Google/Rex platform.

BUG=b:256807255
TEST=Able to program FADT table Bit 21 (Low Power Idle S0)

Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 39fd8e87ff..cbfa49a61d 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -11,6 +11,9 @@ chip soc/intel/meteorlake
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
 
+	# S0ix enable
+	register "s0ix_enable" = "1"
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"