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mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methods 

This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).

TEST=GC6 and GCOFF sequences still work

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Tim Wawrzynczak 2022-08-16 14:22:25 -06:00 committed by Felix Held
parent bcc3059d83
commit e0ddb37ae8
1 changed files with 38 additions and 0 deletions
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38
src/mainboard/google/brya/acpi/power.asl
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
External (\_SB.PCI0.PMC.IPCS, MethodObj)
/* Voltage rail control signals */
#define GPIO_1V8_PWR_EN GPP_E18
@ -21,6 +22,9 @@
/* 250ms in "Timer" units (i.e. 100ns increments) */
#define MIN_OFF_TIME_TIMERS 2500000
#define SRCCLK_DISABLE 0
#define SRCCLK_ENABLE 1
/*
* For board revs 3 and later, the PG pin for the NVVDD VR moved from
* GPP_E16 to GPP_E3. To accommodate this, this DSDT contains a Name
@ -59,6 +63,32 @@ Name (DFCO, 0)
/* GCOFF Timer */
Name (GCOT, 0)
#define PMC_SRCCLK_PIN 0x1
#define PMC_SRCCLK_ENABLE 0x1
#define PMC_SRCCLK_DISABLE 0x0
#define PMC_RP_IDX (1 << 27)
#define PMC_RP_ENABLE (1 << 27)
#define PMC_RP_DISABLE 0x0
/* Control the PCIe SRCCLK# for dGPU */
Method (SRCC, 1, Serialized)
{
If (!Arg0)
{
Local0 = PMC_SRCCLK_DISABLE
Local1 = PMC_RP_DISABLE
}
Else
{
Local0 = PMC_SRCCLK_ENABLE
Local1 = PMC_RP_ENABLE
}
\_SB.PCI0.PMC.IPCS (0xac, 0, 16, PMC_SRCCLK_PIN,
Local0, PMC_RP_IDX, Local1)
}
/* "GC6 In", i.e. GC6 Entry Sequence */
Method (GC6I, 0, Serialized)
{
@ -86,6 +116,9 @@ Method (GC6I, 0, Serialized)
/* Assert GPU_PERST_L */
\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
/* Disable PCIe SRCCLK# */
SRCC (SRCCLK_DISABLE)
Printf ("dGPU entered GC6")
GC6E = GC6_STATE_ENTERED
}
@ -95,6 +128,9 @@ Method (GC6O, 0, Serialized)
{
GC6E = GC6_STATE_TRANSITION
/* Re-enable PCIe SRCCLK# */
SRCC (SRCCLK_ENABLE)
/* Deassert GPU_PERST_L */
\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
@ -230,6 +266,7 @@ Method (NPON, 0, Serialized)
}
Else
{
SRCC (SRCCLK_ENABLE)
PGON ()
\_SB.PCI0.PEG0.LD23 ()
}
@ -252,6 +289,7 @@ Method (NPOF, 0, Serialized)
{
\_SB.PCI0.PEG0.DL23 ()
PGOF ()
SRCC (SRCCLK_DISABLE)
}
}