mainboard/google/poppy: Clean up gpio.h file
1. Update formatting of gpio table to fit everything within 80 column limit. 2. PEN_RESET gpio is non-existent. Get rid of it. BUG=b:37375693 Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh
Furquan Shaikh
parent
55d9c0bd8d
commit
e0f30920f0
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@ -41,202 +41,359 @@
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/* Pad configuration in ramstage */
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */
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/* A0 : RCIN# ==> NC(TP41) */
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/* ESPI_IO0 */
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PAD_CFG_NC(GPP_A0),
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/* ESPI_IO1 */
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/* A1 : ESPI_IO0 */
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/* ESPI_IO2 */
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/* A2 : ESPI_IO1 */
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/* ESPI_IO3 */
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/* A3 : ESPI_IO2 */
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/* ESPI_CS# */
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/* A4 : ESPI_IO3 */
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/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
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/* A5 : ESPI_CS# */
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/* PIRQA# */ PAD_CFG_NC(GPP_A7),
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/* A6 : SERIRQ ==> NC(TP44) */
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/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
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PAD_CFG_NC(GPP_A6),
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/* ESPI_CLK */
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/* A7 : PIRQA# ==> NC */
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/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
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PAD_CFG_NC(GPP_A7),
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/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
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/* A8 : CLKRUN# ==> NC(TP45) */
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/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
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PAD_CFG_NC(GPP_A8),
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/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
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/* A9 : ESPI_CLK */
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/* ESPI_RESET# */
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/* A10 : CLKOUT_LPC1 ==> NC */
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/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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PAD_CFG_NC(GPP_A10),
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A11 : PME# ==> NC(TP67) */
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/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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PAD_CFG_NC(GPP_A11),
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/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
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/* A12 : BM_BUSY# ==> NC */
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/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
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PAD_CFG_NC(GPP_A12),
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/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE,
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/* A13 : SUSWARN# ==> NC */
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PLTRST), /* ACCEL_GYRO_INT_L */
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PAD_CFG_NC(GPP_A13),
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/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
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/* A14 : ESPI_RESET# */
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* A15 : SUSACK# ==> SUSACK_L */
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* A18 : ISH_GP0 ==> NC */
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PAD_CFG_NC(GPP_A18),
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/* A19 : ISH_GP1 ==> NC */
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PAD_CFG_NC(GPP_A19),
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/* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */
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PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),
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/* A21 : ISH_GP3 ==> NC */
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PAD_CFG_NC(GPP_A21),
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/* A22 : ISH_GP4 ==> NC */
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PAD_CFG_NC(GPP_A22),
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/* A23 : ISH_GP5 ==> NC */
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PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */
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/* B0 : CORE_VID0 ==> NC(TP42) */
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */
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PAD_CFG_NC(GPP_B0),
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/* VRALERT# */ PAD_CFG_NC(GPP_B2),
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/* B1 : CORE_VID1 ==> NC(TP43) */
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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PAD_CFG_NC(GPP_B1),
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/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
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/* B2 : VRALERT# ==> NC */
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/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5),
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PAD_CFG_NC(GPP_B2),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */
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/* B3 : CPU_GP2 ==> NC */
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */
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PAD_CFG_NC(GPP_B3),
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/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
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/* B4 : CPU_GP3 ==> NC */
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/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
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PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
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/* B5 : SRCCLKREQ0# ==> NC */
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/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
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PAD_CFG_NC(GPP_B5),
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SPKR */ PAD_CFG_NC(GPP_B14),
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/* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */
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/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
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/* B8 : SRCCLKREQ3# ==> NC */
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/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
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PAD_CFG_NC(GPP_B8),
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/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
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/* B9 : SRCCLKREQ4# ==> NC */
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/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */
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PAD_CFG_NC(GPP_B9),
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/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */
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/* B10 : SRCCLKREQ5# ==> NC */
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/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */
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PAD_CFG_NC(GPP_B10),
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/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */
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/* B11 : EXT_PWR_GATE# ==> NC */
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/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
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PAD_CFG_NC(GPP_B11),
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/* B12 : SLP_S0# ==> SLP_S0_L_G */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> NC */
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PAD_CFG_NC(GPP_B14),
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/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */
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PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* B21 : GSPI1_MISO ==> PCH_SPI_FP_MISO */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */
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PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
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/* B23 : SM1ALERT# ==> NC */
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PAD_CFG_NC(GPP_B23),
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/* SMBCLK */ PAD_CFG_NC(GPP_C0),
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/* C0 : SMBCLK ==> NC */
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/* SMBDATA */ PAD_CFG_NC(GPP_C1),
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PAD_CFG_NC(GPP_C0),
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/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
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/* C1 : SMBDATA ==> NC */
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/* SML0CLK */ PAD_CFG_NC(GPP_C3),
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PAD_CFG_NC(GPP_C1),
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/* SML0DATA */ PAD_CFG_NC(GPP_C4),
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/* C2 : SMBALERT# ==> NC */
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/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
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PAD_CFG_NC(GPP_C2),
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/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
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/* C3 : SML0CLK ==> NC */
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/* SM1DATA */ PAD_CFG_NC(GPP_C7),
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PAD_CFG_NC(GPP_C3),
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/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */
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/* C4 : SML0DATA ==> NC */
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/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */
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PAD_CFG_NC(GPP_C4),
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/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
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/* C5 : SML0ALERT# ==> NC */
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/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
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PAD_CFG_NC(GPP_C5),
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/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
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/* C6 : SM1CLK ==> EC_IN_RW_OD */
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/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
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PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
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/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
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/* C7 : SM1DATA ==> NC */
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/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
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PAD_CFG_NC(GPP_C7),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
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/* C8 : UART0_RXD ==> FP_INT */
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
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PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */
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/* C9 : UART0_TXD ==> FP_RST_ODL */
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */
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PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
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/* C10 : UART0_RTS# ==> NC */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
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PAD_CFG_NC(GPP_C10),
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/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1,
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/* C11 : UART0_CTS# ==> NC */
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DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
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PAD_CFG_NC(GPP_C11),
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/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
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/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
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PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
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PAD_CFG_GPI(GPP_C13, NONE, DEEP),
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/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
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PAD_CFG_GPI(GPP_C14, NONE, DEEP),
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/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
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PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* C18 : I2C1_SDA ==> PCH_I2C1_NFC_3V3_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_NFC_3V3_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_C22, 1, DEEP),
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/* C23 : UART2_CTS# ==> PCH_WP */
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PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
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/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
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/* D0 : SPI1_CS# ==> NC */
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/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */
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PAD_CFG_NC(GPP_D0),
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/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */
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/* D1 : SPI1_CLK ==> PEN_IRQ_L */
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/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */
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PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
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/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
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/* D2 : SPI1_MISO ==> PEN_PDCT_L */
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/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP,
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PAD_CFG_GPI(GPP_D2, NONE, DEEP),
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NF1), /* ISH_SENSOR */
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/* D3 : SPI1_MOSI ==> NC */
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/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP,
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PAD_CFG_NC(GPP_D3),
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NF1), /* ISH_SENSOR */
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/* D4 : FASHTRIG ==> NC */
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/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
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PAD_CFG_NC(GPP_D4),
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/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
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/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
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/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */
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PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
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/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
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/* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
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/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE,
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PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
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PLTRST), /* SPKR_INT_L */
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/* D7 : ISH_I2C1_SDA ==> NC */
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/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
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PAD_CFG_NC(GPP_D7),
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/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
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/* D8 : ISH_I2C1_SCL ==> NC */
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/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
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PAD_CFG_NC(GPP_D8),
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/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */
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/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
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/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
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PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
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/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */
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/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
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/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */
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PAD_CFG_GPO(GPP_D10, 1, DEEP),
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/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */
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/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
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/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */
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PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
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/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
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/* D12 : ISH_SPI_MOSI ==> NC */
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/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */
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PAD_CFG_NC(GPP_D12),
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/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_CFG_NC(GPP_D13),
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/* D14 : ISH_UART0_TXD ==> NC */
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PAD_CFG_NC(GPP_D14),
|
||||||
|
/* D15 : ISH_UART0_RTS# ==> MIC_IRQ_L */
|
||||||
|
PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST),
|
||||||
|
/* D16 : ISH_UART0_CTS# ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_D16),
|
||||||
|
/* D17 : DMIC_CLK1 */
|
||||||
|
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||||
|
/* D18 : DMIC_DATA1 */
|
||||||
|
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||||
|
/* D19 : DMIC_CLK0 */
|
||||||
|
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||||
|
/* D20 : DMIC_DATA0 */
|
||||||
|
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||||
|
/* D21 : SPI1_IO2 ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_D21),
|
||||||
|
/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
|
||||||
|
PAD_CFG_GPO(GPP_D22, 1, DEEP),
|
||||||
|
/* D23 : I2S_MCLK ==> I2S_MCLK_R */
|
||||||
|
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||||
|
|
||||||
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
|
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
|
||||||
PLTRST), /* TPM_INT_L */
|
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
|
||||||
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
|
/* E1 : SATAXPCIE1 ==> NC */
|
||||||
/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
|
PAD_CFG_NC(GPP_E1),
|
||||||
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
|
/* E2 : SATAXPCIE2 ==> NC */
|
||||||
/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */
|
PAD_CFG_NC(GPP_E2),
|
||||||
/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */
|
/* E3 : CPU_GP0 ==> NC */
|
||||||
/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */
|
PAD_CFG_NC(GPP_E3),
|
||||||
/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE,
|
/* E4 : SATA_DEVSLP0 ==> NFC_RESET_ODL */
|
||||||
PLTRST), /* TOUCHSCREEN_INT_L */
|
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||||
/* SATALED# */ PAD_CFG_NC(GPP_E8),
|
/* E5 : SATA_DEVSLP1 ==> NFC_INT_L */
|
||||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
|
PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST),
|
||||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,
|
/* E6 : SATA_DEVSLP2 ==> NFC_FW_DL */
|
||||||
NF1), /* USB_C1_OC_ODL */
|
PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */
|
||||||
/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */
|
/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */
|
||||||
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */
|
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */
|
||||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP,
|
/* E8 : SATALED# ==> NC */
|
||||||
NF1), /* USB_C0_DP_HPD */
|
PAD_CFG_NC(GPP_E8),
|
||||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP,
|
/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
|
||||||
NF1), /* USB_C1_DP_HPD */
|
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), /* SD_CD# */
|
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
|
||||||
/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
|
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
/* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */
|
||||||
/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
|
PAD_CFG_GPO(GPP_E11, 0, DEEP),
|
||||||
/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
|
/* E12 : USB2_OC3# ==> USB2_OC3_L */
|
||||||
/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
|
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||||
/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
|
/* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
|
||||||
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
|
PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
|
||||||
/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
|
/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
|
||||||
|
PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
|
||||||
|
/* E15 : DDPD_HPD2 ==> SD_CD# */
|
||||||
|
PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
|
||||||
|
/* E16 : DDPE_HPD3 ==> NC(TP244) */
|
||||||
|
PAD_CFG_NC(GPP_E16),
|
||||||
|
/* E17 : EDP_HPD */
|
||||||
|
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||||
|
/* E18 : DDPB_CTRLCLK ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E18),
|
||||||
|
/* E19 : DDPB_CTRLDATA ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E19),
|
||||||
|
/* E20 : DDPC_CTRLCLK ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E20),
|
||||||
|
/* E21 : DDPC_CTRLDATA ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E21),
|
||||||
|
/* E22 : DDPD_CTRLCLK ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E22),
|
||||||
|
/* E23 : DDPD_CTRLDATA ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_E23),
|
||||||
|
|
||||||
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
|
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
|
||||||
/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
/* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
|
||||||
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||||
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
/* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
|
||||||
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||||
/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */
|
/* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
|
||||||
/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */
|
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||||
/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */
|
/* F3 : I2S2_RXD */
|
||||||
/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */
|
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||||
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */
|
/* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
|
||||||
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/
|
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
|
||||||
/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */
|
/* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
|
||||||
/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */
|
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
|
||||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
/* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */
|
||||||
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
/* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */
|
||||||
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
/* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */
|
||||||
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
/* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */
|
||||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
/* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */
|
||||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
|
||||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
/* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */
|
||||||
/* RSVD */ PAD_CFG_NC(GPP_F23),
|
PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
|
||||||
|
/* F12 : EMMC_CMD */
|
||||||
|
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||||
|
/* F13 : EMMC_DATA0 */
|
||||||
|
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||||
|
/* F14 : EMMC_DATA1 */
|
||||||
|
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||||
|
/* F15 : EMMC_DATA2 */
|
||||||
|
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||||
|
/* F16 : EMMC_DATA3 */
|
||||||
|
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||||
|
/* F17 : EMMC_DATA4 */
|
||||||
|
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||||
|
/* F18 : EMMC_DATA5 */
|
||||||
|
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||||
|
/* F19 : EMMC_DATA6 */
|
||||||
|
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||||
|
/* F20 : EMMC_DATA7 */
|
||||||
|
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||||
|
/* F21 : EMMC_RCLK */
|
||||||
|
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||||
|
/* F22 : EMMC_CLK */
|
||||||
|
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||||
|
/* F23 : RSVD ==> NC */
|
||||||
|
PAD_CFG_NC(GPP_F23),
|
||||||
|
|
||||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
/* G0 : SD_CMD */
|
||||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
/* G1 : SD_DATA0 */
|
||||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
/* G2 : SD_DATA1 */
|
||||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
/* G3 : SD_DATA2 */
|
||||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||||
|
/* G4 : SD_DATA3 */
|
||||||
|
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||||
|
/* G5 : SD_CD# */
|
||||||
|
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||||
|
/* G6 : SD_CLK */
|
||||||
|
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||||
|
/* G7 : SD_WP */
|
||||||
|
PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
||||||
|
|
||||||
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
/* GPD0: BATLOW# ==> PCH_BATLOW_L */
|
||||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
|
/* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
|
||||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
|
||||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||||
/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */
|
/* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
|
||||||
/* RSVD */ PAD_CFG_NC(GPD7),
|
PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
||||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
/* GPD4: SLP_S3# ==> SLP_S3_L */
|
||||||
/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */
|
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||||
/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */
|
/* GPD5: SLP_S4# ==> SLP_S4_L */
|
||||||
/* LANPHYC */ PAD_CFG_NC(GPD11),
|
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||||
|
/* GPD6: SLP_A# ==> NC(TP26) */
|
||||||
|
PAD_CFG_NC(GPD6),
|
||||||
|
/* GPD7: RSVD ==> NC */
|
||||||
|
PAD_CFG_NC(GPD7),
|
||||||
|
/* GPD8: SUSCLK ==> PCH_SUSCLK */
|
||||||
|
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||||
|
/* GPD9: SLP_WLAN# ==> NC(TP25) */
|
||||||
|
PAD_CFG_NC(GPD9),
|
||||||
|
/* GPD10: SLP_S5# ==> NC(TP15) */
|
||||||
|
PAD_CFG_NC(GPD10), /* TP15 */
|
||||||
|
/* GPD11: LANPHYC ==> NC */
|
||||||
|
PAD_CFG_NC(GPD11),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Early pad configuration in bootblock */
|
/* Early pad configuration in bootblock */
|
||||||
static const struct pad_config early_gpio_table[] = {
|
static const struct pad_config early_gpio_table[] = {
|
||||||
/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
|
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
|
||||||
/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
|
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||||
/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
|
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
|
||||||
/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
|
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||||
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
|
||||||
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
|
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||||
PLTRST), /* TPM_INT_L */
|
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
|
||||||
/* Ensure UART pins are in native mode for H1. */
|
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
|
|
||||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
|
/* Ensure UART pins are in native mode for H1. */
|
||||||
|
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
|
||||||
|
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||||
|
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
|
||||||
|
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||||
|
|
||||||
|
/* C23 : UART2_CTS# ==> PCH_WP */
|
||||||
|
PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
|
||||||
|
|
||||||
|
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
|
||||||
|
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
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