coreboot: check Cr50 PM mode on normal boot
Under some scenarios the key ladder on the Cr50 can get disabled. If this state is detected, trigger a reboot of the Cr50 to restore full TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built coreboot on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. TEST=Performed Cr50 rollback to 0.0.22 which does not support the VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and the coreboot log captures the unsupported command. Tested-by: Keith Short <keithshort@chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
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@ -223,6 +223,9 @@ struct elog_event_mem_cache_update {
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#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01
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#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02
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/* Cr50 reset to enable TPM */
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#define ELOG_TYPE_CR50_NEED_RESET 0xb2
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struct elog_event_extended_event {
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u8 event_type;
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u32 event_complement;
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@ -115,7 +115,7 @@ int get_lid_switch(void)
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return 1;
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}
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void mainboard_cr50_update_reset(void)
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void mainboard_prepare_cr50_reset(void)
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{
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#if ENV_RAMSTAGE
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/* Ensure system powers up after CR50 reset */
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@ -266,6 +266,14 @@ static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body)
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uint16_t *sub_command = command_body;
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switch (*sub_command) {
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case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET:
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/* The 16-bit timeout parameter is optional for the
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* IMMEDIATE_RESET command. However in coreboot, the timeout
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* parameter must be specified.
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*/
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rc |= obuf_write_be16(ob, sub_command[0]);
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rc |= obuf_write_be16(ob, sub_command[1]);
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break;
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case TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS:
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rc |= obuf_write_be16(ob, *sub_command);
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break;
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@ -276,6 +284,18 @@ static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body)
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case TPM2_CR50_SUB_CMD_GET_REC_BTN:
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rc |= obuf_write_be16(ob, *sub_command);
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break;
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case TPM2_CR50_SUB_CMD_TPM_MODE:
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/* The Cr50 TPM_MODE command supports an optional parameter.
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* When the parameter is present the Cr50 will attempt to change
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* the TPM state (enable or disable) and returns the new state
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* in the response. When the parameter is absent, the Cr50
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* returns the current TPM state.
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*
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* coreboot currently only uses the TPM get capability and does
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* not set a new TPM state with the Cr50.
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*/
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rc |= obuf_write_be16(ob, *sub_command);
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break;
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default:
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/* Unsupported subcommand. */
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printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n",
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@ -471,12 +491,16 @@ static int unmarshal_vendor_command(struct ibuf *ib,
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return -1;
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switch (vcr->vc_subcommand) {
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case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET:
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break;
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case TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS:
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break;
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case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON:
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return ibuf_read_be8(ib, &vcr->num_restored_headers);
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case TPM2_CR50_SUB_CMD_GET_REC_BTN:
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return ibuf_read_be8(ib, &vcr->recovery_button_state);
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case TPM2_CR50_SUB_CMD_TPM_MODE:
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return ibuf_read_be8(ib, &vcr->tpm_mode);
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default:
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printk(BIOS_ERR,
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"%s:%d - unsupported vendor command %#04x!\n",
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@ -298,6 +298,7 @@ struct vendor_command_response {
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union {
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uint8_t num_restored_headers;
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uint8_t recovery_button_state;
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uint8_t tpm_mode;
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};
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};
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@ -26,7 +26,7 @@ uint32_t tlcl_cr50_enable_nvcommits(void)
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if (response == NULL || (response && response->hdr.tpm_code)) {
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if (response)
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printk(BIOS_INFO, "%s: failed %x\n", __func__,
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response->hdr.tpm_code);
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response->hdr.tpm_code);
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else
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printk(BIOS_INFO, "%s: failed\n", __func__);
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return TPM_E_IOERROR;
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@ -47,7 +47,7 @@ uint32_t tlcl_cr50_enable_update(uint16_t timeout_ms,
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response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, command_body);
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if (!response || response->hdr.tpm_code)
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return TPM_E_INTERNAL_INCONSISTENCY;
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return TPM_E_IOERROR;
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*num_restored_headers = response->vcr.num_restored_headers;
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return TPM_SUCCESS;
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@ -63,8 +63,67 @@ uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state)
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response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &sub_command);
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if (!response || response->hdr.tpm_code)
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return TPM_E_INTERNAL_INCONSISTENCY;
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return TPM_E_IOERROR;
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*recovery_button_state = response->vcr.recovery_button_state;
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return TPM_SUCCESS;
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}
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uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode)
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{
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struct tpm2_response *response;
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uint16_t mode_command = TPM2_CR50_SUB_CMD_TPM_MODE;
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*tpm_mode = TPM_MODE_INVALID;
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printk(BIOS_INFO, "Reading cr50 TPM mode\n");
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response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command);
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if (!response)
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return TPM_E_IOERROR;
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if (response->hdr.tpm_code == VENDOR_RC_INTERNAL_ERROR) {
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/*
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* The Cr50 returns VENDOR_RC_INTERNAL_ERROR iff the key ladder
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* is disabled. The Cr50 requires a reboot to re-enable the key
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* ladder.
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*/
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return TPM_E_MUST_REBOOT;
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}
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if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) {
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/*
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* Explicitly inform caller when command is not supported
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*/
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return TPM_E_NO_SUCH_COMMAND;
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}
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if (response->hdr.tpm_code) {
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/* Unexpected return code from Cr50 */
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return TPM_E_IOERROR;
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}
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/* TPM command completed without error */
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*tpm_mode = response->vcr.tpm_mode;
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return TPM_SUCCESS;
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}
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uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms)
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{
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struct tpm2_response *response;
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uint16_t reset_command_body[] = {
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TPM2_CR50_SUB_CMD_IMMEDIATE_RESET, timeout_ms};
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/*
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* Issue an immediate reset to the Cr50.
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*/
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printk(BIOS_INFO, "Issuing cr50 reset\n");
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response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND,
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&reset_command_body);
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if (!response)
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return TPM_E_IOERROR;
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return TPM_SUCCESS;
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}
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@ -23,9 +23,35 @@
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to extending generically because the marshaling code is assuming all
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knowledge of all commands. */
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#define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0))
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#define TPM2_CR50_SUB_CMD_IMMEDIATE_RESET (19)
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#define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21)
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#define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24)
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#define TPM2_CR50_SUB_CMD_GET_REC_BTN (29)
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#define TPM2_CR50_SUB_CMD_TPM_MODE (40)
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/* Cr50 vendor-specific error codes. */
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#define VENDOR_RC_ERR 0x00000500
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enum cr50_vendor_rc {
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VENDOR_RC_INTERNAL_ERROR = (VENDOR_RC_ERR | 6),
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VENDOR_RC_NO_SUCH_COMMAND = (VENDOR_RC_ERR | 127),
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};
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enum cr50_tpm_mode {
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/*
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* Default state: TPM is enabled, and may be set to either
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* TPM_MODE_ENABLED or TPM_MODE_DISABLED.
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*/
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TPM_MODE_ENABLED_TENTATIVE = 0,
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/* TPM is enabled, and mode may not be changed. */
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TPM_MODE_ENABLED = 1,
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/* TPM is disabled, and mode may not be changed. */
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TPM_MODE_DISABLED = 2,
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TPM_MODE_INVALID,
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};
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/**
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* CR50 specific tpm command to enable nvmem commits before internal timeout
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*/
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uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state);
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/**
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* CR50 specific TPM command sequence to query the current TPM mode.
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*
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* Returns TPM_SUCCESS if TPM mode command completed, the Cr50 does not need a
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* reboot, and the tpm_mode parameter is set to the current TPM mode.
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* Returns TPM_E_MUST_REBOOT if TPM mode command completed, but the Cr50
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* requires a reboot.
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* Returns TPM_E_NO_SUCH_COMMAND if the Cr50 does not support the command.
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* Other returns value indicate a failure accessing the TPM.
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*/
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uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode);
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/**
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* CR50 specific TPM command sequence to trigger an immediate reset to the Cr50
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* device after the specified timeout in milliseconds. A timeout of zero means
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* "IMMEDIATE REBOOT".
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*
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* Return value indicates success or failure of accessing the TPM.
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*/
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uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms);
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#endif /* CR50_TSS_STRUCTURES_H_ */
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@ -42,5 +42,6 @@
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#define TPM_E_NV_DEFINED ((uint32_t)0x0000500b) /* vboot local */
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#define TPM_E_INVALID_ARG ((uint32_t)0x0000500c)
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#define TPM_E_HASH_ERROR ((uint32_t)0x0000500d)
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#define TPM_E_NO_SUCH_COMMAND ((uint32_t)0x0000500e)
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#endif /* TSS_ERRORS_H_ */
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@ -33,8 +33,11 @@ static inline void mark_watchdog_tombstone(void) { return; }
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static inline void reboot_from_watchdog(void) { return; }
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#endif /* CONFIG_CHROMEOS */
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/* Defined as weak function in cr50_enable_update.c */
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void mainboard_cr50_update_reset(void);
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/**
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* Perform any platform specific actions required prior to resetting the Cr50.
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* Defined as weak function in cr50_enable_update.c
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*/
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void mainboard_prepare_cr50_reset(void);
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struct romstage_handoff;
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@ -23,7 +23,75 @@
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#include <security/vboot/vboot_common.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void __weak mainboard_cr50_update_reset(void) {}
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#define C50_RESET_DELAY_MS 1000
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void __weak mainboard_prepare_cr50_reset(void) {}
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/**
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* Check if the Cr50 TPM state requires a chip reset of the Cr50 device.
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*
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* Returns 0 if the Cr50 TPM state is good or if the TPM_MODE command is
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* unsupported. Returns 1 if the Cr50 was reset.
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*/
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static int cr50_reset_if_needed(uint16_t timeout_ms)
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{
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int ret;
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int cr50_must_reset = 0;
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uint8_t tpm_mode;
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ret = tlcl_cr50_get_tpm_mode(&tpm_mode);
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if (ret == TPM_E_NO_SUCH_COMMAND) {
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printk(BIOS_INFO,
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"Cr50 does not support TPM mode command\n");
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/* Older Cr50 firmware, assume no Cr50 reset is required */
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return 0;
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}
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if (ret == TPM_E_MUST_REBOOT) {
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/*
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* Cr50 indicated a reboot is required to restore TPM
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* functionality.
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*/
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cr50_must_reset = 1;
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} else if (ret != TPM_SUCCESS) {
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/* TPM command failed, continue booting. */
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printk(BIOS_ERR,
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"ERROR: Attempt to get CR50 TPM mode failed: %x\n", ret);
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return 0;
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}
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/* If the TPM mode is not enabled-tentative, then the TPM mode is locked
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* and cannot be changed. Perform a Cr50 reset because vboot may need
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* to disable TPM as part of booting an untrusted OS.
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*
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* This is not an expected state, as the Cr50 always sets the TPM mode
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* to TPM_MODE_ENABLED_TENTATIVE during any TPM reset action.
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*/
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if (tpm_mode != TPM_MODE_ENABLED_TENTATIVE) {
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printk(BIOS_NOTICE,
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"NOTICE: Unexpected Cr50 TPM mode (%d). "
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"A Cr50 reset is required.\n", tpm_mode);
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cr50_must_reset = 1;
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}
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/* If TPM state is okay, no reset needed. */
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if (!cr50_must_reset)
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return 0;
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ret = tlcl_cr50_immediate_reset(timeout_ms);
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if (ret != TPM_SUCCESS) {
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/* TPM command failed, continue booting. */
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printk(BIOS_ERR,
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"ERROR: Attempt to reset CR50 failed: %x\n",
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ret);
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return 0;
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}
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/* Cr50 is about to be reset, caller needs to prepare */
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return 1;
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}
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static void enable_update(void *unused)
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{
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ret = tlcl_lib_init();
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if (ret != VB2_SUCCESS) {
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printk(BIOS_ERR, "tlcl_lib_init() failed for CR50 update: %x\n",
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ret);
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printk(BIOS_ERR,
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"ERROR: tlcl_lib_init() failed for CR50 update: %x\n",
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ret);
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return;
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}
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/* Reboot in 1000 ms if necessary. */
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ret = tlcl_cr50_enable_update(1000, &num_restored_headers);
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ret = tlcl_cr50_enable_update(C50_RESET_DELAY_MS,
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&num_restored_headers);
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if (ret != TPM_SUCCESS) {
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printk(BIOS_ERR, "Attempt to enable CR50 update failed: %x\n",
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ret);
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printk(BIOS_ERR,
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"ERROR: Attempt to enable CR50 update failed: %x\n",
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ret);
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return;
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}
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/* If no headers were restored there is no reset forthcoming. */
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if (!num_restored_headers)
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return;
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if (!num_restored_headers) {
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/* If no headers were restored there is no reset forthcoming due
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* to a Cr50 firmware update. Also check if the Cr50 TPM mode
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* requires a reset.
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*
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* TODO: to eliminate a TPM command during every boot, the
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* TURN_UPDATE_ON command could be enhanced/replaced in the Cr50
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* firmware to perform the TPM mode/key-ladder check in addition
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* to the FW version check.
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*/
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/*
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* If the Cr50 was not reset, continue booting.
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*/
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if (!cr50_reset_if_needed(C50_RESET_DELAY_MS))
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return;
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printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n");
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elog_add_event(ELOG_TYPE_CR50_NEED_RESET);
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} else {
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printk(BIOS_INFO,
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"Waiting for CR50 reset to pick up update.\n");
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elog_add_event(ELOG_TYPE_CR50_UPDATE);
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}
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/* Give mainboard a chance to take action */
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mainboard_cr50_update_reset();
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elog_add_event(ELOG_TYPE_CR50_UPDATE);
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mainboard_prepare_cr50_reset();
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/* clear current post code avoid chatty eventlog on subsequent boot*/
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post_code(0);
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printk(BIOS_INFO, "Waiting for CR50 reset to pick up update.\n");
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if (IS_ENABLED(CONFIG_POWER_OFF_ON_CR50_UPDATE))
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poweroff();
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halt();
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