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mb/hp/z220_series: Add Z220 CMT Workstation variant 

This is based on previous work done by a good friend of mine.

The notable differences between this board and the SFF variant is that:
 - CMT has 4 more PCI/PCIe ports than SFF.
 - CMT has 2 more SATA ports than SFF.

TESTED on Z220 CMT Workstation (boots to payload)

Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Damien Zammit 2022-03-15 19:37:50 +11:00 committed by Martin L Roth
parent 598ff42f12
commit e0ff2735f3
4 changed files with 200 additions and 0 deletions
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5
src/mainboard/hp/z220_series/Kconfig
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@ -18,6 +18,9 @@ config BOARD_HP_Z220_SERIES_COMMON
select GFX_GMA_ANALOG_I2C_HDMI_B select GFX_GMA_ANALOG_I2C_HDMI_B
select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_GBE_REGION
config BOARD_HP_Z220_CMT_WORKSTATION
select BOARD_HP_Z220_SERIES_COMMON
config BOARD_HP_Z220_SFF_WORKSTATION config BOARD_HP_Z220_SFF_WORKSTATION
select BOARD_HP_Z220_SERIES_COMMON select BOARD_HP_Z220_SERIES_COMMON
@ -42,9 +45,11 @@ config MAINBOARD_DIR
default "hp/z220_series" default "hp/z220_series"
config VARIANT_DIR config VARIANT_DIR
default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION
default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION
default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE

3
src/mainboard/hp/z220_series/Kconfig.name
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@ -1,2 +1,5 @@
config BOARD_HP_Z220_CMT_WORKSTATION
bool "Z220 CMT Workstation"
config BOARD_HP_Z220_SFF_WORKSTATION config BOARD_HP_Z220_SFF_WORKSTATION
bool "Z220 SFF Workstation" bool "Z220 SFF Workstation"

177
src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c Normal file
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@ -0,0 +1,177 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_NATIVE,
.gpio3 = GPIO_MODE_NATIVE,
.gpio4 = GPIO_MODE_NATIVE,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_NATIVE,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_NATIVE,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_NATIVE,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_OUTPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio15 = GPIO_LEVEL_LOW,
.gpio17 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_NATIVE,
.gpio51 = GPIO_MODE_NATIVE,
.gpio52 = GPIO_MODE_NATIVE,
.gpio53 = GPIO_MODE_NATIVE,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_NATIVE,
.gpio61 = GPIO_MODE_GPIO,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_INPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio61 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_OUTPUT,
.gpio72 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio71 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};

15
src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb Normal file
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@ -0,0 +1,15 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1791 inherit
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0x3f"
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3
device pci 1c.3 on end # PCIe Port #4
device pci 1c.5 on end # PCIe Port #6
end
end
end