GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Kontron 986LCD-M updates: 

* ACPI updates: MCFG, HPET, FADT
* some mptable fixes for certain riser cards
* Use Channel XOR randomization
* Fix SuperIO HWM setup
* Enable all three network adapters

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-03-11 15:20:36 +00:00 committed by Stefan Reinauer
parent cc44b06d9d
commit e1025d0f7f
4 changed files with 57 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
src/mainboard/kontron/986lcd-m/acpi_tables.c
View File

@ -96,30 +96,50 @@ void acpi_create_oemb(acpi_oemb_t *oemb)
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
#if 0
device_t dev; device_t dev;
u64 mmcfg; u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 dev = dev_find_device(0x8086, 0x27a0, 0);
if (!dev) if (!dev)
return current; return current;
// MMCFG not supported or not enabled. // MMCFG not supported or not enabled.
if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0) pciexbar_reg=pci_read_config32(dev, 0x48);
if (!(pciexbar_reg & (1 << 0)))
return current; return current;
mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28; switch ((pciexbar_reg >> 1) & 3) {
if (!mmcfg) case 0: // 256MB
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
max_buses = 256;
break;
case 1: // 128M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
max_buses = 128;
break;
case 2: // 64M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
}
if (!pciexbar)
return current; return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff); current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
#endif pciexbar, 0x0, 0x0, max_buses - 1);
return current; return current;
} }
void acpi_create_intel_hpet(acpi_hpet_t * hpet) void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{ {
#define HPET_ADDR 0xfe800000ULL #define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header); acpi_header_t *header = &(hpet->header);
acpi_addr_t *addr = &(hpet->addr); acpi_addr_t *addr = &(hpet->addr);
@ -135,16 +155,15 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet)
header->revision = 1; header->revision = 1;
/* fill out HPET address */ /* fill out HPET address */
// XXX factory bios just puts an address here -- who's right?
addr->space_id = 0; /* Memory */ addr->space_id = 0; /* Memory */
addr->bit_width = 64; addr->bit_width = 64;
addr->bit_offset = 0; addr->bit_offset = 0;
addr->addrl = HPET_ADDR & 0xffffffff; addr->addrl = HPET_ADDR & 0xffffffff;
addr->addrh = HPET_ADDR >> 32; addr->addrh = HPET_ADDR >> 32;
hpet->id = 0x80861234; /* VIA */ hpet->id = 0x8086a201; /* Intel */
hpet->number = 0x00; hpet->number = 0x00;
hpet->min_tick = 0x0090; hpet->min_tick = 0x0080;
header->checksum = header->checksum =
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
@ -199,10 +218,11 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_oemb_t *oemb; acpi_oemb_t *oemb;
acpi_header_t *dsdt; acpi_header_t *dsdt;
/* Align ACPI tables to 16byte */
start = (start + 0x0f) & -0x10;
current = start; current = start;
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
printk_info("ACPI: Writing ACPI tables at %lx.\n", start); printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */ /* We need at least an RSDP and an RSDT Table */
@ -222,7 +242,6 @@ unsigned long write_acpi_tables(unsigned long start)
/* /*
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
#if 0
printk_debug("ACPI: * HPET\n"); printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
@ -230,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start)
ALIGN_CURRENT; ALIGN_CURRENT;
acpi_create_intel_hpet(hpet); acpi_create_intel_hpet(hpet);
acpi_add_table(rsdt, hpet); acpi_add_table(rsdt, hpet);
#endif
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n"); printk_debug("ACPI: * MADT\n");
@ -239,14 +258,13 @@ unsigned long write_acpi_tables(unsigned long start)
current += madt->header.length; current += madt->header.length;
ALIGN_CURRENT; ALIGN_CURRENT;
acpi_add_table(rsdt, madt); acpi_add_table(rsdt, madt);
#if 0
printk_debug("ACPI: * MCFG\n"); printk_debug("ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current; mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg); acpi_create_mcfg(mcfg);
current += mcfg->header.length; current += mcfg->header.length;
ALIGN_CURRENT; ALIGN_CURRENT;
acpi_add_table(rsdt, mcfg); acpi_add_table(rsdt, mcfg);
#endif
printk_debug("ACPI: * OEMB\n"); printk_debug("ACPI: * OEMB\n");
oemb=(acpi_oemb_t *)current; oemb=(acpi_oemb_t *)current;
@ -278,10 +296,10 @@ unsigned long write_acpi_tables(unsigned long start)
/* We patched up the DSDT, so we need to recalculate the checksum */ /* We patched up the DSDT, so we need to recalculate the checksum */
dsdt->checksum = 0; dsdt->checksum = 0;
dsdt->checksum = acpi_checksum(dsdt, dsdt->length); dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
#endif #endif
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length); dsdt->length);
printk_debug("ACPI: * FADT\n"); printk_debug("ACPI: * FADT\n");
@ -291,7 +309,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_create_fadt(fadt, facs, dsdt); acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdt, fadt); acpi_add_table(rsdt, fadt);
printk_debug("current = %x\n", current); printk_debug("current = %lx\n", current);
printk_debug("ACPI: * DMI (Linux workaround)\n"); printk_debug("ACPI: * DMI (Linux workaround)\n");
memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);

9
src/mainboard/kontron/986lcd-m/auto.c
View File

@ -64,7 +64,7 @@ static void setup_ich7_gpios(void)
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */ /* Input Control Registers */
outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
} }
@ -85,6 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
* #define will do. * #define will do.
*/ */
#define OVERRIDE_CLOCK_DISABLE 1 #define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c" #include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c" #include "northbridge/intel/i945/reset_test.c"
@ -100,7 +102,7 @@ static void ich7_enable_lpc(void)
// Enable COM1/COM2/KBD/SuperIO1+2 // Enable COM1/COM2/KBD/SuperIO1+2
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
// Enable HWM at 0xa00 // Enable HWM at 0xa00
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
// COM3 decode // COM3 decode
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
// COM4 decode // COM4 decode
@ -236,7 +238,8 @@ static void rcba_config(void)
RCBA32(0x3400) = (1 << 2); RCBA32(0x3400) = (1 << 2);
/* Disable unused devices */ /* Disable unused devices */
RCBA32(0x3418) = 0x000e0063; RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Enable PCIe Root Port Clock Gate */ /* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001; // RCBA32(0x341c) = 0x00000001;

10
src/mainboard/kontron/986lcd-m/fadt.c
View File

@ -31,15 +31,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4); memcpy(header->signature, "FACP", 4);
header->length = 132; header->length = 132;
header->revision = 1; header->revision = 2;
memcpy(header->oem_id, "CORE ", 6); memcpy(header->oem_id, "CORE ", 6);
memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, "CORE", 4); memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 0; header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long) facs; fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt; fadt->dsdt = (unsigned long) dsdt;
fadt->preferred_pm_profile = 0; fadt->model = 1;
fadt->preferred_pm_profile = 2;
fadt->sci_int = 0x9; fadt->sci_int = 0x9;
fadt->smi_cmd = 0xb2; fadt->smi_cmd = 0xb2;
fadt->acpi_enable = 0xe1; fadt->acpi_enable = 0xe1;
@ -58,7 +59,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->pm1_evt_len = 4; fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2; fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1; fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4; fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8; fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0; fadt->gpe1_blk_len = 0;
@ -79,6 +80,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
// all cpus support c1 // all cpus support c1
// sleep button is generic // sleep button is generic
// rtc wakeup/s4 not possible // rtc wakeup/s4 not possible
// use platform timer
header->checksum = header->checksum =
acpi_checksum((void *) fadt, header->length); acpi_checksum((void *) fadt, header->length);

6
src/mainboard/kontron/986lcd-m/mptable.c
View File

@ -100,6 +100,7 @@ void *smp_write_config_table(void *v)
/* Firewire 4:0.0 */ /* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
/* Old riser card */
// riser slot top 5:8.0 // riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
// riser slot middle 5:9.0 // riser slot middle 5:9.0
@ -107,6 +108,11 @@ void *smp_write_config_table(void *v)
// riser slot bottom 5:a.0 // riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
/* Onboard Ethernet */ /* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);