Kontron 986LCD-M updates:
* ACPI updates: MCFG, HPET, FADT * some mptable fixes for certain riser cards * Use Channel XOR randomization * Fix SuperIO HWM setup * Enable all three network adapters Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
cc44b06d9d
commit
e1025d0f7f
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@ -96,30 +96,50 @@ void acpi_create_oemb(acpi_oemb_t *oemb)
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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#if 0
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device_t dev;
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u64 mmcfg;
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0
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dev = dev_find_device(0x8086, 0x27a0, 0);
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if (!dev)
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return current;
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// MMCFG not supported or not enabled.
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if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0)
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pciexbar_reg=pci_read_config32(dev, 0x48);
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28;
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if (!mmcfg)
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
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max_buses = 256;
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break;
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case 1: // 128M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
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max_buses = 128;
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break;
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case 2: // 64M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
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max_buses = 64;
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break;
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default: // RSVD
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return current;
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}
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if (!pciexbar)
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff);
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#endif
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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pciexbar, 0x0, 0x0, max_buses - 1);
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return current;
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}
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void acpi_create_intel_hpet(acpi_hpet_t * hpet)
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{
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#define HPET_ADDR 0xfe800000ULL
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#define HPET_ADDR 0xfed00000ULL
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acpi_header_t *header = &(hpet->header);
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acpi_addr_t *addr = &(hpet->addr);
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@ -135,16 +155,15 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet)
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header->revision = 1;
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/* fill out HPET address */
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// XXX factory bios just puts an address here -- who's right?
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addr->space_id = 0; /* Memory */
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addr->bit_width = 64;
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addr->bit_offset = 0;
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addr->addrl = HPET_ADDR & 0xffffffff;
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addr->addrh = HPET_ADDR >> 32;
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hpet->id = 0x80861234; /* VIA */
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hpet->id = 0x8086a201; /* Intel */
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hpet->number = 0x00;
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hpet->min_tick = 0x0090;
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hpet->min_tick = 0x0080;
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header->checksum =
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acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
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@ -199,10 +218,11 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_oemb_t *oemb;
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acpi_header_t *dsdt;
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/* Align ACPI tables to 16byte */
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start = (start + 0x0f) & -0x10;
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current = start;
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/* Align ACPI tables to 16byte */
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ALIGN_CURRENT;
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printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
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/* We need at least an RSDP and an RSDT Table */
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@ -222,7 +242,6 @@ unsigned long write_acpi_tables(unsigned long start)
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/*
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* We explicitly add these tables later on:
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*/
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#if 0
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printk_debug("ACPI: * HPET\n");
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hpet = (acpi_hpet_t *) current;
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@ -230,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start)
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ALIGN_CURRENT;
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acpi_create_intel_hpet(hpet);
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acpi_add_table(rsdt, hpet);
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#endif
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/* If we want to use HPET Timers Linux wants an MADT */
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printk_debug("ACPI: * MADT\n");
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@ -239,14 +258,13 @@ unsigned long write_acpi_tables(unsigned long start)
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current += madt->header.length;
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ALIGN_CURRENT;
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acpi_add_table(rsdt, madt);
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#if 0
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printk_debug("ACPI: * MCFG\n");
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mcfg = (acpi_mcfg_t *) current;
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acpi_create_mcfg(mcfg);
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current += mcfg->header.length;
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ALIGN_CURRENT;
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acpi_add_table(rsdt, mcfg);
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#endif
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printk_debug("ACPI: * OEMB\n");
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oemb=(acpi_oemb_t *)current;
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@ -278,10 +296,10 @@ unsigned long write_acpi_tables(unsigned long start)
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/* We patched up the DSDT, so we need to recalculate the checksum */
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dsdt->checksum = 0;
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dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
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dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
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#endif
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printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
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printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
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dsdt->length);
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printk_debug("ACPI: * FADT\n");
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@ -291,7 +309,7 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdt, fadt);
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printk_debug("current = %x\n", current);
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printk_debug("current = %lx\n", current);
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printk_debug("ACPI: * DMI (Linux workaround)\n");
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memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
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@ -64,7 +64,7 @@ static void setup_ich7_gpios(void)
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outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
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/* Input Control Registers */
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outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
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outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
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outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
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outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
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outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
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}
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@ -85,6 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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* #define will do.
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*/
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#define OVERRIDE_CLOCK_DISABLE 1
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#define CHANNEL_XOR_RANDOMIZATION 1
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#include "northbridge/intel/i945/raminit.h"
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#include "northbridge/intel/i945/raminit.c"
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#include "northbridge/intel/i945/reset_test.c"
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@ -100,7 +102,7 @@ static void ich7_enable_lpc(void)
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// Enable COM1/COM2/KBD/SuperIO1+2
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
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// Enable HWM at 0xa00
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
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// COM3 decode
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
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// COM4 decode
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@ -236,7 +238,8 @@ static void rcba_config(void)
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RCBA32(0x3400) = (1 << 2);
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/* Disable unused devices */
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RCBA32(0x3418) = 0x000e0063;
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RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
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RCBA32(0x3418) |= (1 << 0); // Required.
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/* Enable PCIe Root Port Clock Gate */
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// RCBA32(0x341c) = 0x00000001;
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@ -31,15 +31,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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memset((void *) fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = 132;
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header->revision = 1;
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header->revision = 2;
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memcpy(header->oem_id, "CORE ", 6);
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memcpy(header->oem_table_id, "COREBOOT", 8);
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memcpy(header->asl_compiler_id, "CORE", 4);
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header->asl_compiler_revision = 0;
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header->asl_compiler_revision = 1;
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fadt->firmware_ctrl = (unsigned long) facs;
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fadt->dsdt = (unsigned long) dsdt;
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fadt->preferred_pm_profile = 0;
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fadt->model = 1;
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fadt->preferred_pm_profile = 2;
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fadt->sci_int = 0x9;
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fadt->smi_cmd = 0xb2;
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fadt->acpi_enable = 0xe1;
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@ -58,7 +59,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm2_cnt_len = 0;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->gpe1_blk_len = 0;
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@ -79,6 +80,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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// all cpus support c1
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// sleep button is generic
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// rtc wakeup/s4 not possible
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// use platform timer
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header->checksum =
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acpi_checksum((void *) fadt, header->length);
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@ -100,6 +100,7 @@ void *smp_write_config_table(void *v)
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/* Firewire 4:0.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
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/* Old riser card */
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// riser slot top 5:8.0
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
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// riser slot middle 5:9.0
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@ -107,6 +108,11 @@ void *smp_write_config_table(void *v)
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// riser slot bottom 5:a.0
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
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/* New Riser Card */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
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/* Onboard Ethernet */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
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