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soc/mediatek/mt8195: Update clock square setting 

To reduce suspend power consumption,
1. Disable unused CLKSQ2.
2. Set CLKSQ_EN to sleep control for SPM 26M sleep control.
   No bus clock when enter 26m sleep control, and only control
   clock square by side band.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chun-Jie Chen 2021-08-13 09:23:25 +08:00 committed by Hung-Te Lin
parent 8316db207d
commit e1028d5ee3
1 changed files with 8 additions and 2 deletions
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10
src/soc/mediatek/mt8195/pll.c
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@ -638,12 +638,18 @@ void mt_pll_init(void)
int i; int i;
/* enable clock square */ /* enable clock square */
setbits32(&mtk_apmixed->ap_pll_con0, 0x4); setbits32(&mtk_apmixed->ap_pll_con0, BIT(2));
udelay(PLL_CKSQ_ON_DELAY); udelay(PLL_CKSQ_ON_DELAY);
/* enable clock square1 low-pass filter */ /* enable clock square1 low-pass filter */
setbits32(&mtk_apmixed->ap_pll_con0, 0x2); setbits32(&mtk_apmixed->ap_pll_con0, BIT(1));
/*
* BIT(3): 1 for register control; 0 for sleep control
* BIT(8): 1 to enable clock square2; 0 to disable it
*/
clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8));
/* xPLL PWR ON */ /* xPLL PWR ON */
for (i = 0; i < APMIXED_PLL_MAX; i++) for (i = 0; i < APMIXED_PLL_MAX; i++)