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soc/intel/skylake: Refactor ternary expressions 

To be consistent with the rest of the tree, replace all left ternary
expressions, which are used for device enablement / disablement,
with `dev && dev->enabled`.

Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-08-11 06:34:15 +02:00 committed by Michael Niewöhner
parent ffa710b9dd
commit e104934a23
2 changed files with 10 additions and 10 deletions
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16
src/soc/intel/skylake/chip.c
View File

@ -167,7 +167,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
dev = pcidev_path_on_root(PCH_DEVFN_SATA);
params->SataEnable = dev ? dev->enabled : 0;
params->SataEnable = dev && dev->enabled;
if (params->SataEnable) {
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
@ -236,7 +236,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev ? dev->enabled : 0;
params->Heci3Enabled = dev && dev->enabled;
params->LogoPtr = config->LogoPtr;
params->LogoSize = config->LogoSize;
@ -248,7 +248,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
dev = pcidev_path_on_root(PCH_DEVFN_GBE);
params->PchLanEnable = dev ? dev->enabled : 0;
params->PchLanEnable = dev && dev->enabled;
if (params->PchLanEnable) {
params->PchLanLtrEnable = config->EnableLanLtr;
params->PchLanK1OffEnable = config->EnableLanK1Off;
@ -258,7 +258,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SsicPortEnable = config->SsicPortEnable;
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
params->ScsEmmcEnabled = dev ? dev->enabled : 0;
params->ScsEmmcEnabled = dev && dev->enabled;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
@ -275,10 +275,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* If ISH is enabled, enable ISH elements */
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
params->PchIshEnable = dev ? dev->enabled : 0;
params->PchIshEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_HDA);
params->PchHdaEnable = dev ? dev->enabled : 0;
params->PchHdaEnable = dev && dev->enabled;
params->PchHdaVcType = config->PchHdaVcType;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
@ -353,7 +353,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Show SPI controller if enabled in devicetree.cb */
dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev ? dev->enabled : 0;
params->ShowSpiController = dev && dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
@ -367,7 +367,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable or disable Gaussian Mixture Model in devicetree */
dev = pcidev_path_on_root(SA_DEVFN_GMM);
params->GmmEnable = dev ? dev->enabled : 0;
params->GmmEnable = dev && dev->enabled;
/*
* Send VR specific mailbox commands:

4
src/soc/intel/skylake/romstage/romstage.c
View File

@ -295,13 +295,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_t_cfg->PchDciEn = config->PchDciEn;
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
m_cfg->EnableTraceHub = dev ? dev->enabled : 0;
m_cfg->EnableTraceHub = dev && dev->enabled;
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller */
dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
m_cfg->SmbusEnable = dev ? dev->enabled : 0;
m_cfg->SmbusEnable = dev && dev->enabled;
/* Set primary graphic device */
soc_primary_gfx_config_params(m_cfg, config);