mb/google/volteer/malefor: Enable touch screen

Enable Goodix touch screen and ensure it works properly.

BUG=b:154191288
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the Goodix touch screen function.

Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598
Reviewed-by: Alex Levin <levinale@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
William Wei 2020-04-22 16:23:16 +08:00 committed by Patrick Georgi
parent 7023174b88
commit e11072e6c7
2 changed files with 21 additions and 3 deletions

View File

@ -19,7 +19,7 @@ static const struct pad_config gpio_table[] = {
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
PAD_CFG_GPO(GPP_A7, 1, DEEP),
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
PAD_CFG_GPO(GPP_A8, 0, DEEP),
/* A9 : I2S2_TXD ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_A9, NONE, DEEP),
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
@ -121,7 +121,7 @@ static const struct pad_config gpio_table[] = {
/* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* C10 : UART0_RTS# ==> USI_RST_L */
PAD_CFG_GPO(GPP_C10, 1, DEEP),
PAD_CFG_GPO(GPP_C10, 0, DEEP),
/* C11 : UART0_CTS# ==> NOT USED */
PAD_NC(GPP_C11, NONE),
/* C12 : UART1_RXD ==> MEM_STRAP_0 */
@ -205,7 +205,7 @@ static const struct pad_config gpio_table[] = {
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
PAD_NC(GPP_E6, NONE),
/* E7 : CPU_GP1 ==> USI_INT */
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
/* E8 : SPI1_CS1# ==> SLP_S0IX */
PAD_CFG_GPO(GPP_E8, 0, DEEP),
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */

View File

@ -1,6 +1,24 @@
chip soc/intel/tigerlake
device domain 0 on
device pci 15.1 on
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
end # I2C1
end
end