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drivers/intel/fsp1_1: Print the MTRR's FSP-T set up 

Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2019-01-12 11:48:37 +01:00 committed by Patrick Georgi
parent ec3c8b552d
commit e124fa5a9d
1 changed files with 2 additions and 0 deletions
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src/drivers/intel/fsp1_1/car.c
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@ -64,6 +64,8 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
display_mtrrs();
if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
car_params->bootloader_car_end != car_params->bootloader_car_end !=
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {