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mb/google/volteer/variants: Enable RTD3 for the NVMe device 

Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.

Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.

BUG=b:160996445
TEST=tested on delbin

Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie 2020-10-10 00:50:32 +00:00 committed by Duncan Laurie
parent e997d85e3b
commit e1490e55ed
6 changed files with 36 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/volteer/variants/delbin/gpio.c
View File

@ -27,8 +27,8 @@ static const struct pad_config override_gpio_table[] = {
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */

8
src/mainboard/google/volteer/variants/delbin/overridetree.cb
View File

@ -148,6 +148,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end
end
end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.

8
src/mainboard/google/volteer/variants/terrador/overridetree.cb
View File

@ -179,6 +179,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end
end
end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.

2
src/mainboard/google/volteer/variants/volteer2/gpio.c
View File

@ -29,6 +29,8 @@ static const struct pad_config override_gpio_table[] = {
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
/* B5 : ISH_I2C0_CVF_SDA */

8
src/mainboard/google/volteer/variants/volteer2/overridetree.cb
View File

@ -281,6 +281,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end
end
end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.

8
src/mainboard/google/volteer/variants/voxel/overridetree.cb
View File

@ -194,6 +194,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end
end
end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.