superio/nuvoton/npcd378: Switch to superio/common
Replace DSDT ACPI code and DSDT injection with a SSDT only solution. The current implementation shows some issues on current Linux, which might be due to external ACPI objects, which are then injected into DSDT or the fact that those objects only use 3 characters. Replace all the DSDT code with an SSDT generator. Tested on HP Z220: Boots into Linux with no ACPI errors. The SSDT can be disassembled. Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph
Felix Held
parent
56626cf5d8
commit
e1498ce6da
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@ -15,6 +15,7 @@
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Method(_WAK, 1, NotSerialized)
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{
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// Generated by SSDT
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\_SB.PCI0.LPCB.SIO0.SIOW (Arg0)
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Return(Package(){0,0})
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@ -22,5 +23,6 @@ Method(_WAK, 1, NotSerialized)
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Method(_PTS, 1, NotSerialized)
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{
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// Generated by SSDT
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\_SB.PCI0.LPCB.SIO0.SIOS (Arg0)
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}
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@ -13,24 +13,10 @@
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* GNU General Public License for more details.
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*/
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define SUPERIO_SHOW_SP2
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#define SUPERIO_SHOW_KBC
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#include <superio/nuvoton/npcd378/acpi/superio.asl>
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Scope (\_GPE)
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{
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Method (_L08, 0, NotSerialized)
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{
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\_SB.PCI0.LPCB.SIO0.SIOH ()
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}
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Method (_L0D, 0, NotSerialized)
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{
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Notify (\_SB.PCI0.EHC1, 0x02)
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@ -75,6 +75,8 @@ chip northbridge/intel/sandybridge
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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chip superio/common
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device pnp 2e.ff on # passes SIO base addr to SSDT gen
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chip superio/nuvoton/npcd378
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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@ -88,8 +90,8 @@ chip northbridge/intel/sandybridge
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irq 0x1a = 0xb0
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# dumped from superiotool:
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irq 0x1b = 0x1e
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irq 0x27 = 0x04
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irq 0x2a = 0x00
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irq 0x27 = 0x08
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irq 0x2a = 0x20
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irq 0x2d = 0x01
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# parallel port
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io 0x60 = 0x378
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@ -171,6 +173,8 @@ chip northbridge/intel/sandybridge
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#drq 0xfe = 0x03
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end
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end
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end
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end
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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@ -15,6 +15,7 @@
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Method(_WAK, 1, NotSerialized)
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{
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// Generated by SSDT
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\_SB.PCI0.LPCB.SIO0.SIOW (Arg0)
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Return(Package(){0,0})
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@ -22,5 +23,6 @@ Method(_WAK, 1, NotSerialized)
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Method(_PTS, 1, NotSerialized)
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{
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// Generated by SSDT
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\_SB.PCI0.LPCB.SIO0.SIOS (Arg0)
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}
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@ -13,24 +13,10 @@
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* GNU General Public License for more details.
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*/
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define SUPERIO_SHOW_SP2
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#define SUPERIO_SHOW_KBC
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#include <superio/nuvoton/npcd378/acpi/superio.asl>
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Scope (\_GPE)
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{
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Method (_L08, 0, NotSerialized)
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{
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\_SB.PCI0.LPCB.SIO0.SIOH ()
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}
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Method (_L0D, 0, NotSerialized)
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{
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Notify (\_SB.PCI0.EHC1, 0x02)
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@ -76,6 +76,8 @@ chip northbridge/intel/sandybridge
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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chip superio/common
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device pnp 2e.ff on # passes SIO base addr to SSDT gen
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chip superio/nuvoton/npcd378
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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@ -172,6 +174,8 @@ chip northbridge/intel/sandybridge
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#drq 0xfe = 0x03
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end
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end
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end
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end
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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@ -2,3 +2,5 @@
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# This file is part of the coreboot project.
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ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c
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ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += ../../common/ssdt.c
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ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += ../../common/generic.c
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@ -1,321 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the NPCD378 SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x2 SP1 Implemented, untested
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* 0x5 KBCK Implemented, untested
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME NPCD378
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("Nuvoton NPCD378 Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8,
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}
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IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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ACT1, 1, /* Logical device activation */
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ACT2, 1, /* Logical device activation */
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ACT3, 1, /* Logical device activation */
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ACT4, 1, /* Logical device activation */
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ACT5, 1, /* Logical device activation */
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ACT6, 1, /* Logical device activation */
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ACT7, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef SUPERIO_SHOW_LPT
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 1
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef SUPERIO_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SUPERIO_SHOW_SP2
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 3
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SUPERIO_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_PS2LDN 5
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#define SUPERIO_KBC_LDN 6
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef SUPERIO_SHOW_GPIO
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 8
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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// generated by SSDT
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External(SWB, IntObj)
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External(SWL, IntObj)
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OperationRegion (SWCR, SystemIO, SWB, SWL)
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Field (SWCR, ByteAcc, NoLock, Preserve)
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{
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LEDC, 8,
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SWCC, 8
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}
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// generated by SSDT
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External(RNB, IntObj)
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External(RNL, IntObj)
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OperationRegion (RNTR, SystemIO, RNB, RNL)
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Field (RNTR, ByteAcc, NoLock, Preserve)
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{
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GPES, 8,
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GPEE, 8,
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Offset (0x08),
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GPS0, 8,
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GPS1, 8,
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GPS2, 8,
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GPS3, 8,
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GPE0, 8,
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GPE1, 8,
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GPE2, 8,
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GPE3, 8
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}
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Name (MSFG, One)
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Name (KBFG, One)
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Name (PMFG, Zero) // Wake event backup
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Method (_CRS, 0, Serialized)
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{
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Name (CRS, ResourceTemplate ()
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{
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FixedIO (SUPERIO_PNP_BASE, 0x02)
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// filled below
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FixedIO (0, 0, CRS1)
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FixedIO (0, 0, CRS2)
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})
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CreateWordField (CRS, CRS1._BAS, TMP1)
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Store(SWB, TMP1)
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CreateByteField (CRS, CRS1._LEN, TMP2)
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Store(SWL, TMP2)
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CreateWordField (CRS, CRS2._BAS, TMP3)
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Store(RNB, TMP3)
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CreateByteField (CRS, CRS2._LEN, TMP4)
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Store(RNL, TMP4)
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/* Announce the used I/O ports to the OS */
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Return (CRS)
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}
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#ifdef SUPERIO_SHOW_KBC
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#if defined(SUPERIO_KBC_LDN)
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#define _PS2_KB SUPERIO_ID(KBD, SUPERIO_KBC_LDN)
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#else
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#define _PS2_KB PS2K
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#endif
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Scope (_PS2_KB)
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{
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Method (_PSW, 1, NotSerialized)
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{
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KBFG = Arg0
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}
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x08, 0x03})
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}
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}
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#if defined(SUPERIO_KBC_PS2M)
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#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2M)
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#elif defined(SUPERIO_KBC_PS2LDN)
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#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)
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#else
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#define _PS2_M PS2M
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#endif
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Scope (_PS2_M)
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{
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Method (_PSW, 1, NotSerialized)
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{
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MSFG = Arg0
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}
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x08, 0x03})
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}
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}
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Method (SIOH, 0, NotSerialized)
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{
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If ((PMFG & 0xE8))
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{
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Notify (_PS2_KB, 0x02)
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}
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If ((PMFG & 0x10))
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{
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Notify (_PS2_M, 0x02)
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}
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}
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#else
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Method (SIOH, 0, NotSerialized)
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{
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}
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#endif
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/* SuperIO sleep method */
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Method (SIOS, 1, NotSerialized)
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{
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If ((0x05 != Arg0))
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{
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/* Set PS/2 powerstate in S3 */
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If (KBFG)
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{
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GPE2 |= 0xE8
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}
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Else
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{
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GPE2 &= 0x17
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}
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If (MSFG)
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{
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GPE2 |= 0x10
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}
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Else
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{
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GPE2 &= 0xEF
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}
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/* Enable wake on GPE */
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GPEE = One
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If ((0x03 == Arg0))
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{
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/* green LED fading */
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Local1 = LEDC
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Local1 &= 0xE0
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LEDC = (Local1 | 0x1C)
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Local1 = SWCC
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Local1 &= 0xBF
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SWCC = (Local1 | 0x40)
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}
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}
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GPE0 = 0x10
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GPE1 = 0x20
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}
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/* SuperIO wake method */
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Method (SIOW, 1, NotSerialized)
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{
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/* Store wake status */
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PMFG = GPS2
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/* Disable wake on GPE */
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GPEE = Zero
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GPE0 = Zero
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GPE1 = Zero
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/* green LED normal */
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Local1 = LEDC
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Local1 &= 0xE0
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LEDC = (Local1 | 0x1E)
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Local1 = SWCC
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SWCC = (Local1 & 0xBF)
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}
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}
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External (\_SB.PCI0.LPCB.SIO0, DeviceObj)
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External (\_SB.PCI0.LPCB.SIO0.SIOS, MethodObj)
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External (\_SB.PCI0.LPCB.SIO0.SIOW, MethodObj)
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|
|
@ -10,6 +10,8 @@
|
|||
#include <superio/conf_mode.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <superio/common/ssdt.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "npcd378.h"
|
||||
|
||||
|
|
@ -87,49 +89,337 @@ static void npcd378_init(struct device *dev)
|
|||
}
|
||||
|
||||
#if CONFIG(HAVE_ACPI_TABLES)
|
||||
static void npcd378_ssdt(struct device *dev)
|
||||
/* Provide ACPI HIDs for generic Super I/O SSDT */
|
||||
static const char *npcd378_acpi_hid(const struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
/* Sanity checks */
|
||||
if (dev->path.type != DEVICE_PATH_PNP)
|
||||
return NULL;
|
||||
if (dev->path.pnp.port == 0)
|
||||
return NULL;
|
||||
if ((dev->path.pnp.device & 0xff) > NPCD378_GPIOA)
|
||||
return NULL;
|
||||
|
||||
const char *scope = acpi_device_path(dev);
|
||||
if (!scope) {
|
||||
printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev));
|
||||
return;
|
||||
switch (dev->path.pnp.device & 0xff) {
|
||||
case NPCD378_FDC:
|
||||
return ACPI_HID_FDC;
|
||||
case NPCD378_PP:
|
||||
return ACPI_HID_LPT;
|
||||
case NPCD378_SP1: /* fallthrough */
|
||||
case NPCD378_SP2:
|
||||
return ACPI_HID_COM;
|
||||
case NPCD378_AUX:
|
||||
return ACPI_HID_MOUSE;
|
||||
case NPCD378_KBC:
|
||||
return ACPI_HID_KEYBOARD;
|
||||
default:
|
||||
return ACPI_HID_PNP;
|
||||
}
|
||||
}
|
||||
|
||||
static void npcd378_ssdt_aux(struct device *dev)
|
||||
{
|
||||
/* Scope */
|
||||
acpigen_write_scope(acpi_device_path(dev));
|
||||
|
||||
acpigen_write_method("_PSW", 1);
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_emit_namestring("^^MSFG");
|
||||
acpigen_pop_len(); /* Pop Method */
|
||||
|
||||
acpigen_write_PRW(8, 3);
|
||||
|
||||
acpigen_pop_len(); /* Pop Scope */
|
||||
}
|
||||
|
||||
static void npcd378_ssdt_kbc(struct device *dev)
|
||||
{
|
||||
/* Scope */
|
||||
acpigen_write_scope(acpi_device_path(dev));
|
||||
|
||||
acpigen_write_method("_PSW", 1);
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_emit_namestring("^^KBFG");
|
||||
acpigen_pop_len(); /* Pop Method */
|
||||
|
||||
acpigen_write_PRW(8, 3);
|
||||
|
||||
acpigen_pop_len(); /* Pop Scope */
|
||||
}
|
||||
|
||||
static void npcd378_ssdt_pwr(struct device *dev)
|
||||
{
|
||||
const char *name = acpi_device_path(dev);
|
||||
const char *scope = acpi_device_scope(dev);
|
||||
char *tmp_name;
|
||||
|
||||
/* Scope */
|
||||
acpigen_write_scope(name);
|
||||
|
||||
acpigen_emit_ext_op(OPREGION_OP);
|
||||
acpigen_emit_namestring("SWCR");
|
||||
acpigen_emit_byte(SYSTEMIO);
|
||||
acpigen_emit_namestring("IO0B");
|
||||
acpigen_emit_namestring("IO0S");
|
||||
|
||||
struct fieldlist l1[] = {
|
||||
FIELDLIST_OFFSET(0),
|
||||
FIELDLIST_NAMESTR("LEDC", 8),
|
||||
FIELDLIST_NAMESTR("SWCC", 8),
|
||||
};
|
||||
|
||||
acpigen_write_field("SWCR", l1, ARRAY_SIZE(l1), FIELD_BYTEACC |
|
||||
FIELD_NOLOCK | FIELD_PRESERVE);
|
||||
|
||||
acpigen_emit_ext_op(OPREGION_OP);
|
||||
acpigen_emit_namestring("RNTR");
|
||||
acpigen_emit_byte(SYSTEMIO);
|
||||
acpigen_emit_namestring("IO1B");
|
||||
acpigen_emit_namestring("IO1S");
|
||||
|
||||
struct fieldlist l2[] = {
|
||||
FIELDLIST_OFFSET(0),
|
||||
FIELDLIST_NAMESTR("GPES", 8),
|
||||
FIELDLIST_NAMESTR("GPEE", 8),
|
||||
FIELDLIST_OFFSET(8),
|
||||
FIELDLIST_NAMESTR("GPS0", 8),
|
||||
FIELDLIST_NAMESTR("GPS1", 8),
|
||||
FIELDLIST_NAMESTR("GPS2", 8),
|
||||
FIELDLIST_NAMESTR("GPS3", 8),
|
||||
FIELDLIST_NAMESTR("GPE0", 8),
|
||||
FIELDLIST_NAMESTR("GPE1", 8),
|
||||
FIELDLIST_NAMESTR("GPE2", 8),
|
||||
FIELDLIST_NAMESTR("GPE3", 8),
|
||||
};
|
||||
|
||||
acpigen_write_field("RNTR", l2, ARRAY_SIZE(l2), FIELD_BYTEACC |
|
||||
FIELD_NOLOCK | FIELD_PRESERVE);
|
||||
|
||||
/* Method (SIOW, 1, NotSerialized) */
|
||||
acpigen_write_method("SIOW", 1);
|
||||
acpigen_write_store();
|
||||
acpigen_emit_namestring("^GPS2");
|
||||
acpigen_emit_namestring("^^PMFG");
|
||||
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
acpigen_emit_namestring("^GPEE");
|
||||
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
acpigen_emit_namestring("^GPE0");
|
||||
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
acpigen_emit_namestring("^GPE1");
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^LEDC");
|
||||
acpigen_write_integer(0xE0);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
|
||||
acpigen_emit_byte(OR_OP);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
acpigen_write_integer(0x1E);
|
||||
acpigen_emit_namestring("^LEDC");
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^SWCC");
|
||||
acpigen_write_integer(0xBF);
|
||||
acpigen_emit_namestring("^SWCC");
|
||||
|
||||
acpigen_pop_len(); /* SIOW method */
|
||||
|
||||
/* Method (SIOS, 1, NotSerialized) */
|
||||
acpigen_write_method("SIOS", 1);
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LNOT_OP);
|
||||
acpigen_emit_byte(LEQUAL_OP);
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_write_integer(5);
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LEQUAL_OP);
|
||||
acpigen_emit_namestring("^^KBFG");
|
||||
acpigen_emit_byte(ONE_OP);
|
||||
|
||||
acpigen_emit_byte(OR_OP);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
acpigen_write_integer(0xE8);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
acpigen_write_else();
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
acpigen_write_integer(0x17);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
|
||||
acpigen_pop_len(); /* Pop Else */
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LEQUAL_OP);
|
||||
acpigen_emit_namestring("^^MSFG");
|
||||
acpigen_emit_byte(ONE_OP);
|
||||
|
||||
acpigen_emit_byte(OR_OP);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
acpigen_write_integer(0x10);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
acpigen_write_else();
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
acpigen_write_integer(0xEF);
|
||||
acpigen_emit_namestring("^GPE2");
|
||||
|
||||
acpigen_pop_len(); /* Pop Else */
|
||||
|
||||
/* Enable wake on GPE */
|
||||
acpigen_write_store();
|
||||
acpigen_emit_byte(ONE_OP);
|
||||
acpigen_emit_namestring("^GPEE");
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LEQUAL_OP);
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_write_integer(3);
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^LEDC");
|
||||
acpigen_write_integer(0xE0);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
|
||||
acpigen_emit_byte(OR_OP);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
acpigen_write_integer(0x1C);
|
||||
acpigen_emit_namestring("^LEDC");
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
acpigen_emit_namestring("^SWCC");
|
||||
acpigen_write_integer(0xBF);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
|
||||
acpigen_emit_byte(OR_OP);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
acpigen_write_integer(0x40);
|
||||
acpigen_emit_namestring("^SWCC");
|
||||
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
|
||||
acpigen_write_store();
|
||||
acpigen_write_integer(0x10);
|
||||
acpigen_emit_namestring("^GPE0");
|
||||
|
||||
acpigen_write_store();
|
||||
acpigen_write_integer(0x20);
|
||||
acpigen_emit_namestring("^GPE1");
|
||||
|
||||
acpigen_pop_len(); /* Pop SIOS method */
|
||||
|
||||
acpigen_pop_len(); /* Pop Scope */
|
||||
|
||||
/* Inject into parent: */
|
||||
acpigen_write_scope(acpi_device_scope(dev));
|
||||
|
||||
acpigen_write_name_integer("MSFG", 1);
|
||||
acpigen_write_name_integer("KBFG", 1);
|
||||
acpigen_write_name_integer("PMFG", 0);
|
||||
|
||||
/* DSDT must call SIOW on _WAK */
|
||||
/* Method (SIOW, 1, NotSerialized) */
|
||||
acpigen_write_method("SIOW", 1);
|
||||
acpigen_emit_byte(RETURN_OP);
|
||||
tmp_name = strconcat(name, ".SIOW");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_pop_len();
|
||||
|
||||
/* DSDT must call SIOS on _PTS */
|
||||
/* Method (SIOS, 1, NotSerialized) */
|
||||
acpigen_write_method("SIOS", 1);
|
||||
acpigen_emit_byte(RETURN_OP);
|
||||
tmp_name = strconcat(name, ".SIOS");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
acpigen_emit_byte(ARG0_OP);
|
||||
acpigen_pop_len(); /* Pop Method */
|
||||
|
||||
acpigen_pop_len(); /* Scope */
|
||||
|
||||
acpigen_write_scope("\\_GPE");
|
||||
|
||||
/* Method (SIOH, 0, NotSerialized) */
|
||||
acpigen_write_method("_L08", 0);
|
||||
acpigen_emit_byte(AND_OP);
|
||||
tmp_name = strconcat(scope, ".PMFG");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
acpigen_write_integer(0xE8);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LGREATER_OP);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
|
||||
acpigen_emit_byte(NOTIFY_OP);
|
||||
tmp_name = strconcat(scope, ".L060");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
acpigen_write_integer(2);
|
||||
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
|
||||
acpigen_emit_byte(AND_OP);
|
||||
tmp_name = strconcat(scope, ".PMFG");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
acpigen_write_integer(0x10);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
|
||||
acpigen_write_if();
|
||||
acpigen_emit_byte(LGREATER_OP);
|
||||
acpigen_emit_byte(LOCAL0_OP);
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
|
||||
acpigen_emit_byte(NOTIFY_OP);
|
||||
tmp_name = strconcat(scope, ".L050");
|
||||
acpigen_emit_namestring(tmp_name);
|
||||
free(tmp_name);
|
||||
acpigen_write_integer(2);
|
||||
acpigen_pop_len(); /* Pop If */
|
||||
|
||||
acpigen_pop_len(); /* Pop Method */
|
||||
|
||||
acpigen_pop_len(); /* Scope */
|
||||
}
|
||||
|
||||
static void npcd378_fill_ssdt_generator(struct device *dev)
|
||||
{
|
||||
superio_common_fill_ssdt_generator(dev);
|
||||
|
||||
switch (dev->path.pnp.device) {
|
||||
case NPCD378_PWR: {
|
||||
res = find_resource(dev, PNP_IDX_IO0);
|
||||
if (!res || !res->base) {
|
||||
printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n",
|
||||
NPCD378_PWR);
|
||||
case NPCD378_PWR:
|
||||
npcd378_ssdt_pwr(dev);
|
||||
break;
|
||||
case NPCD378_AUX:
|
||||
npcd378_ssdt_aux(dev);
|
||||
break;
|
||||
case NPCD378_KBC:
|
||||
npcd378_ssdt_kbc(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
acpigen_write_scope(scope);
|
||||
acpigen_write_name_integer("SWB", res->base);
|
||||
acpigen_write_name_integer("SWL", res->size);
|
||||
acpigen_pop_len(); /* pop scope */
|
||||
|
||||
res = find_resource(dev, PNP_IDX_IO1);
|
||||
if (!res || !res->base) {
|
||||
printk(BIOS_ERR, "NPCD378: LDN%u IOBASE2 not set.\n",
|
||||
NPCD378_PWR);
|
||||
break;
|
||||
}
|
||||
|
||||
acpigen_write_scope(scope);
|
||||
acpigen_write_name_integer("RNB", res->base);
|
||||
acpigen_write_name_integer("RNL", res->size);
|
||||
acpigen_pop_len(); /* pop scope */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const char *npcd378_acpi_name(const struct device *dev)
|
||||
{
|
||||
return "SIO0";
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -141,8 +431,9 @@ static struct device_operations ops = {
|
|||
.init = npcd378_init,
|
||||
.ops_pnp_mode = &pnp_conf_mode_8787_aa,
|
||||
#if CONFIG(HAVE_ACPI_TABLES)
|
||||
.acpi_fill_ssdt_generator = npcd378_ssdt,
|
||||
.acpi_name = npcd378_acpi_name,
|
||||
.acpi_fill_ssdt_generator = npcd378_fill_ssdt_generator,
|
||||
.acpi_name = superio_common_ldn_acpi_name,
|
||||
.acpi_hid = npcd378_acpi_hid,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue