From e14e66bc0c14f1cb73ac480101025a37c2412773 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 9 Nov 2021 15:21:45 -0700 Subject: [PATCH] soc/amd/cezanne: enable LPC decodes if platform uses LPC Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Signed-off-by: Jeremy Soller Reviewed-on: https://review.coreboot.org/c/coreboot/+/59103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/cezanne/early_fch.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 586e80cbd0..3addcf8c5d 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -20,6 +20,12 @@ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), }; +static void lpc_configure_decodes(void) +{ + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) + lpc_enable_port80(); +} + static void reset_i2c_peripherals(void) { const struct soc_amd_cezanne_config *cfg = config_of_soc(); @@ -45,6 +51,9 @@ void fch_pre_init(void) if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) configure_espi_with_mb_hook(); + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + lpc_configure_decodes(); + fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io();