Also improve boot time on AMD for the DDR3 code path.

Fix a typo, too.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Arne Georg Gleditsch 2010-09-09 10:35:52 +00:00 committed by Patrick Georgi
parent 6556534bab
commit e150e9a571
2 changed files with 2 additions and 2 deletions

View File

@ -3189,7 +3189,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n"); print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
/* ClrClToNB_D postponed til we're done executing from ROM */ /* ClrClToNB_D postponed until we're done executing from ROM */
mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
} }

View File

@ -2873,7 +2873,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat) struct DCTStatStruc *pDCTstat)
{ {
mct_ClrClToNB_D(pMCTstat, pDCTstat); /* ClrClToNB_D postponed until we're done executing from ROM */
mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
} }