Also improve boot time on AMD for the DDR3 code path.
Fix a typo, too. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -3189,7 +3189,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
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print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
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print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
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/* ClrClToNB_D postponed til we're done executing from ROM */
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/* ClrClToNB_D postponed until we're done executing from ROM */
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mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
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mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
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}
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}
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@ -2873,7 +2873,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
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static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
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static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat)
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struct DCTStatStruc *pDCTstat)
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{
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{
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mct_ClrClToNB_D(pMCTstat, pDCTstat);
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/* ClrClToNB_D postponed until we're done executing from ROM */
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mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
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mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
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}
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}
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