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soc/intel: Fix bad uses of __SIMPLE_DEVICE__ 

Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.

Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.

Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2018-12-29 08:04:16 +02:00
parent e2c653e049
commit e16c9df454
6 changed files with 3 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/broadwell/smihandler.c
View File

@ -80,12 +80,8 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
if (val == 0xffffffff || val == 0x00000000 ||

8
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -167,11 +167,7 @@ bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
*/
static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
{
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
uint8_t bc_cntl;
assert(IS_POWER_OF_2(bios_cntl_bit));
@ -214,11 +210,7 @@ void lpc_set_eiss(void)
*/
void lpc_set_serirq_mode(enum serirq_mode mode)
{
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
uint8_t scnt;
scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);

5
src/soc/intel/common/block/smm/smihandler.c
View File

@ -134,11 +134,8 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
if (!smihandler_soc_disable_busmaster(dev))
continue;

4
src/soc/intel/denverton_ns/bootblock/uart.c
View File

@ -31,11 +31,7 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
u32 mmio_base)
{
register uint16_t reg16;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);
#else
struct device *uart_dev = PCI_DEV(bus, dev, func);
#endif
/* We're using MMIO for HSUARTs. This section is needed for logging
* from FSP only

8
src/soc/intel/denverton_ns/romstage.c
View File

@ -49,11 +49,7 @@ static void display_fsp_smbios_memory_info_hob(void)
static void early_pmc_init(void)
{
/* PMC (B0:D31:F2). */
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_PMC_DEV;
#else
struct device *dev = PCH_PMC_DEV;
#endif
/* Is PMC present */
if (pci_read_config16(dev, 0) == 0xffff) {
@ -102,11 +98,7 @@ static void early_pmc_init(void)
static void early_tco_init(void)
{
/* SMBUS (B0:D31:F4). */
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#else
struct device *dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#endif
/* Configure TCO base address */
if (pci_read_config16(dev, TCOBASE) == 0xffff) {

6
src/soc/intel/denverton_ns/smihandler.c
View File

@ -65,12 +65,8 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
if (val == 0xffffffff || val == 0x00000000 ||