soc/intel: Factor out common smbus.h
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
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19af7bc822
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 6
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*/
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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#ifndef _SOC_ALDERLAKE_SMBUS_H_
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#define _SOC_ALDERLAKE_SMBUS_H_
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/* IO and MMIO registers under primary BAR */
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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@ -1,27 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CANNONLAKE_SMBUS_H_
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#define _SOC_CANNONLAKE_SMBUS_H_
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _INTELPCH_SMBUS_H_
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#define _INTELPCH_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#endif
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@ -1,29 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_ELKHARTLAKE_SMBUS_H_
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#define _SOC_ELKHARTLAKE_SMBUS_H_
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* IO and MMIO registers under primary BAR */
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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@ -1,27 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_ICELAKE_SMBUS_H_
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#define _SOC_ICELAKE_SMBUS_H_
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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@ -1,29 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_JASPERLAKE_SMBUS_H_
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#define _SOC_JASPERLAKE_SMBUS_H_
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* IO and MMIO registers under primary BAR */
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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@ -3,25 +3,6 @@
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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@ -1,35 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 6
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*/
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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#ifndef _SOC_TIGERLAKE_SMBUS_H_
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#define _SOC_TIGERLAKE_SMBUS_H_
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/* IO and MMIO registers under primary BAR */
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#include <intelpch/smbus.h>
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#endif
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