src: change coreboot to lowercase

The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/riscv/sbi.S

@@ -58,7 +58,7 @@ sbi_page:
 	.align 4
 
 	/* -1984: int sbi_console_getchar(void); */
-	li a0, -1	/* failure: Coreboot doesn't support console input */
+	li a0, -1	/* failure: coreboot doesn't support console input */
 	jr ra
 	.align 4
 

src/arch/riscv/trap_handler.c

@@ -180,7 +180,7 @@ static void interrupt_handler(trapframe *tf)
 		break;
 	default:
 		printk(BIOS_EMERG, "======================================\n");
-		printk(BIOS_EMERG, "Coreboot: Unknown machine interrupt: 0x%llx\n",
+		printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n",
 		       cause);
 		printk(BIOS_EMERG, "======================================\n");
 		print_trap_information(tf);
@@ -222,7 +222,7 @@ void trap_handler(trapframe *tf)
 			break;
 		default:
 			printk(BIOS_EMERG, "================================\n");
-			printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n");
+			printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
 			printk(BIOS_EMERG, "================================\n");
 			print_trap_information(tf);
 			break;

src/cpu/amd/car/cache_as_ram.inc

@@ -45,7 +45,7 @@
  *   xmm2: Fam10h comparison value
  *   xmm3: Fam15h comparison value
  *   xmm4: Backup EBX
- *   xmm5: Coreboot init detect
+ *   xmm5: coreboot init detect
  */
 
 	/* Save the BIST result. */

src/cpu/amd/family_10h-family_15h/fidvid.c

@@ -60,7 +60,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
     by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
     if the warm reset is issued by coreboot to update NbFid. So it is required
     or not ? How can I tell who issued warm reset ?
-    Coreboot transitions to P0 instead, which is not recommended, and does
+    coreboot transitions to P0 instead, which is not recommended, and does
     not follow 2.4.2.15.2 to do so.
 
 9.- TODO Requires information on current delivery capability

src/cpu/amd/quadcore/quadcore_id.c

@@ -105,7 +105,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 		}
 	}
 	if (fam15h && dual_node) {
-		/* Coreboot expects each separate processor die to be on a different nodeid.
+		/* coreboot expects each separate processor die to be on a different nodeid.
 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
 		 */
 		uint32_t f5x84;
@@ -123,7 +123,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 			id.coreid = id.coreid - core_count;
 		}
 	} else if (rev_gte_d && dual_node) {
-		/* Coreboot expects each separate processor die to be on a different nodeid.
+		/* coreboot expects each separate processor die to be on a different nodeid.
 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
 		 */
 		uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1;

src/drivers/aspeed/common/ast_dp501.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * File taken from the Linux ast driver (v3.18.5)
- * Coreboot-specific includes added at top and/or contents modified
+ * coreboot-specific includes added at top and/or contents modified
  * as needed to function within the coreboot environment.
  *
  * This program is free software; you can redistribute it and/or modify

src/drivers/aspeed/common/ast_dram_tables.h

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * File taken from the Linux ast driver (v3.18.5)
- * Coreboot-specific includes added at top and/or contents modified
+ * coreboot-specific includes added at top and/or contents modified
  * as needed to function within the coreboot environment.
  *
  * This program is free software; you can redistribute it and/or modify

src/drivers/intel/fsp1_1/cache_as_ram.inc

@@ -137,7 +137,7 @@ CAR_init_done:
 	/* Save FSP_INFO_HEADER location in ebx */
 	mov	%ebp, %ebx
 
-	/* Coreboot assumes stack/heap region will be zero */
+	/* coreboot assumes stack/heap region will be zero */
 	cld
 	movl	%ecx, %edi
 	neg	%ecx

src/drivers/intel/fsp1_1/raminit.c

@@ -277,7 +277,7 @@ void raminit(struct romstage_params *params)
 
 	/* Verify the FSP 1.1 HOB interface */
 	if (fsp_verification_failure)
-		die("ERROR - Coreboot's requirements not met by FSP binary!\n");
+		die("ERROR - coreboot's requirements not met by FSP binary!\n");
 
 	/* Display the memory configuration */
 	report_memory_config();

src/drivers/xgi/common/XGI_main.h

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

src/drivers/xgi/common/vb_init.c

@@ -4,7 +4,7 @@
  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  *
  * File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
  * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode
  *
  * This program is free software; you can redistribute it and/or modify

src/drivers/xgi/common/vb_setmode.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

src/drivers/xgi/common/vb_util.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

src/ec/quanta/ene_kb3940q/acpi/ec.asl

@@ -63,7 +63,7 @@ Device (EC0)
 		BTBD, 1,        // Battery Malfunction                  ; 70h.3
 		ACMD, 1,        // ACPI Mode                            ; 70h.4
 		    , 1,        // Reserved                             ; 70h.5
-		SSBS, 1,        // 1=Standard BIOS, 0=Coreboot          ; 70h.6
+		SSBS, 1,        // 1=Standard BIOS, 0=coreboot          ; 70h.6
 		PSTH, 1,        // Passive Thermal Policy               ; 70h.7
 		BST0, 8,        // Battery Status                       ; 71h
 		                // Bit0 : Discharging

src/include/console/post_codes.h

@@ -329,7 +329,7 @@
 /**
  * \brief Elfload fail or die() called
  *
- * Coreboot was not able to load the payload, no payload was detected
+ * coreboot was not able to load the payload, no payload was detected
  * or die() was called.
  * \n
  * If this code appears before entering ramstage, then most likely

src/include/memrange.h

@@ -21,7 +21,7 @@
  * is exposed so that a memranges can be used on the stack if needed. */
 struct memranges {
 	struct range_entry *entries;
-	/* Coreboot doesn't have a free() function. Therefore, keep a cache of
+	/* coreboot doesn't have a free() function. Therefore, keep a cache of
 	 * free'd entries.  */
 	struct range_entry *free_list;
 };

src/include/types.h

@@ -26,7 +26,7 @@
 #define BIT(x)				(1ul << (x))
 
 /**
- * Coreboot error codes
+ * coreboot error codes
  *
  * When building functions that return a status or an error code, use cb_err as
  * the return type. When failure reason needs to be communicated by the return

src/lib/selfboot.c

@@ -73,7 +73,7 @@ static void segment_insert_after(struct segment *seg, struct segment *new)
  *
  * Benefits:
  * - Nearly arbitrary standalone executables can be loaded.
- * - Coreboot is preserved, so it can be returned to.
+ * - coreboot is preserved, so it can be returned to.
  * - The implementation is still relatively simple,
  *   and much simpler than the general case implemented in kexec.
  */

src/mainboard/amd/inagua/broadcom.c

@@ -26,7 +26,7 @@
 
 #include <types.h>
 #include <console/console.h>
-#include <device/device.h>	//Coreboot device access
+#include <device/device.h>	//coreboot device access
 #include <device/pci.h>
 #include <delay.h>
 #include <endian.h>

src/mainboard/pcengines/alix2d/romstage.c

@@ -105,7 +105,7 @@ static void mb_gpio_init(void)
 	 * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
 	 *       may be used here, but not after PCI Init.
 	 * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
-	 *       leds-alix2.c driver. Coreboot dynamically assigns this space,
+	 *       leds-alix2.c driver. coreboot dynamically assigns this space,
 	 *       so the driver does not work anymore.
 	 *       Good workaround: use the newer driver
 	 *       Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100

src/northbridge/via/vx900/early_vx900.c

@@ -102,7 +102,7 @@ void vx900_disable_auto_reboot(void)
  * \brief Disables 'shadowing' of system ROM
  *
  * Disable unnecessary shadowing of the ROM in the first 1MB of address space.
- * Coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
+ * coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
  * This function frees the entire 640k-1M range for DRAM. VGA may still use
  * the 640k-768k range, if enabled later.
  */

src/soc/intel/apollolake/acpi/globalnvs.asl

@@ -33,7 +33,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,      // 0x02 - LID State
 	PWRS,	8,      // 0x03 - AC Power State
 	DPTE,	8,      // 0x04 - Enable DPTF
-	CBMC,	32,     // 0x05 - 0x08 - Coreboot Memory Console
+	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
 	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
 	NHLA,	64,     // 0x19 - 0x20 - NHLT Address

src/soc/intel/apollolake/include/soc/nvs.h

@@ -33,7 +33,7 @@ typedef struct global_nvs_t {
 	uint8_t		lids; /* 0x02 - LID State */
 	uint8_t		pwrs; /* 0x03 - AC Power State */
 	uint8_t		dpte; /* 0x04 - Enable DPTF */
-	uint32_t	cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
+	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
 	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */

src/soc/intel/broadwell/acpi/globalnvs.asl

@@ -55,7 +55,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,	// 0x16 - LID State
 	PWRS,	8,	// 0x17 - AC Power State
 	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
+	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 

src/soc/intel/broadwell/include/soc/nvs.h

@@ -46,7 +46,7 @@ typedef struct {
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
 	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 	u8	unused[208];

src/soc/intel/skylake/acpi/globalnvs.asl

@@ -57,7 +57,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,	// 0x16 - LID State
 	PWRS,	8,	// 0x17 - AC Power State
 	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
+	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 	DPTE,	8,	// 0x30 - Enable DPTF

src/soc/intel/skylake/chip.c

@@ -182,7 +182,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	 * To disable Heci, the Psf needs to be left unlocked
 	 * by FSP after end of post sequence. Based on the devicetree
 	 * setting, we set the appropriate PsfUnlock policy in Fsp,
-	 * do the changes and then lock it back in Coreboot
+	 * do the changes and then lock it back in coreboot
 	 *
 	 */
 	if (config->HeciEnabled == 0)

src/soc/intel/skylake/cpu.c

@@ -226,7 +226,7 @@ static void configure_isst(void)
 	if (conf->speed_shift_enable) {
 		/*
 		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		  is supported or not. Coreboot needs to configure MSR 0x1AA
+		  is supported or not. coreboot needs to configure MSR 0x1AA
 		  which is then reflected in the CPUID register.
 		*/
 		msr = rdmsr(MSR_MISC_PWR_MGMT);

src/soc/intel/skylake/include/soc/nvs.h

@@ -47,7 +47,7 @@ typedef struct {
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
 	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 	u8	dpte; /* 0x30 - Enable DPTF */

src/soc/samsung/exynos5250/alternate_cbfs.c

@@ -26,7 +26,7 @@
 #include <symbols.h>
 
 /* This allows USB A-A firmware upload from a compatible host in four parts:
- * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * The first two are the bare BL1 and the coreboot boot block, which are just
  * written to their respective loading addresses. These transfers are initiated
  * by the IROM / BL1, so this code has nothing to do with them.
  *

src/soc/samsung/exynos5420/alternate_cbfs.c

@@ -27,7 +27,7 @@
 #include <symbols.h>
 
 /* This allows USB A-A firmware upload from a compatible host in four parts:
- * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * The first two are the bare BL1 and the coreboot boot block, which are just
  * written to their respective loading addresses. These transfers are initiated
  * by the IROM / BL1, so this code has nothing to do with them.
  *

src/soc/samsung/exynos5420/smp.c

@@ -182,7 +182,7 @@ static void core_start_execution(void)
 
 	if (cpu_state & CORE_STATE_RESET) {
 		/* For Reset, U-Boot jumps to its starting address;
-		 * on Coreboot, seems ok to ignore for now. */
+		 * on coreboot, seems ok to ignore for now. */
 	}
 	wait_and_jump(&exynos_cpu_states->hotplug_address);
 	/* never returns. */

src/southbridge/intel/common/firmware/Makefile.inc

@@ -41,7 +41,7 @@ endif
 add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
 ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+	printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
 	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
 	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
 	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"

src/vendorcode/amd/cimx/sb700/SBCMN.c

@@ -145,7 +145,7 @@ void    commonInitEarlyBoot(AMDSBCFG* pConfig) {
         RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
 
 
-        #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+        #if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot.
         //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
         //changing it.
         ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);

src/vendorcode/amd/cimx/sb700/SBPort.c

@@ -222,7 +222,7 @@ void  sbPowerOnInit (AMDSBCFG *pConfig){
   if (dbVar0 > 4) {
     dbVar0 = 0;
   }
-  //KZ [061811]-It's used wrong BIOS SIZE for Coreboot.  RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+  //KZ [061811]-It's used wrong BIOS SIZE for coreboot.  RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
 
   if (pConfig->Spi33Mhz)
     //spi reg0c[13:12] to 01h  to run spi 33Mhz in system bios