arch/armv7: Add API to disable MMU pages.

Disables 4K regions in the MMU table.
Assumes that the region is already accounted for by the first level page table entry.

BRANCH=storm
BUG=chrome-os-partner:24786
TEST=verified mmu.pagetable.list output for Storm:

_______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________|
     C:00000000--00000FFF|                         |   |   |         |                                |    |    |                                |
     C:00001000--000FFFFF|  A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
     C:00100000--29FFFFFF|  A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
     C:2A000000--2A05FFFF|  A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
     C:2A060000--2A0FFFFF|  A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
     C:2A100000--3FFFFFFF|  A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
     C:40000000--59FFFFFF|  A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
     C:5A000000--5A1FFFFF|  A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
     C:5A200000--7FFFFFFF|  A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
     C:80000000--FFFFFFFF|                         |   |   |         |                                |    |    |                                |

Change-Id: Ib603da91966cc4c70ea9d5fee04f1e9890d0bb93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67db80e6476d8ed35f0a9d1e0d3ca03612b9d9be
Original-Change-Id: I6b149c7edbd975231b783cc53ddb63cf2e94052c
Original-Signed-off-by: Vikas Das <vdas@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/253800
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org>
Reviewed-on: http://review.coreboot.org/9912
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/arch/arm/armv7/mmu.c

@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  * Copyright 2013 Google Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -185,7 +186,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry)
 	return table;
 }
 
-void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
+static pte_t *mmu_validate_create_sub_table(u32 start_kb, u32 size_kb)
 {
 	pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE/KiB)];
 	pte_t *table = (void *)(uintptr_t)(*pgd_entry & NEXTLEVEL_MASK);
@@ -197,6 +198,13 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 	if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL)
 		table = mmu_create_subtable(pgd_entry);
 
+	return table;
+}
+
+void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
+{
+	pte_t *table = mmu_validate_create_sub_table(start_kb, size_kb);
+
 	/* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */
 	pte_t attr = attrs[policy].value;
 	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
@@ -211,6 +219,19 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 		       (start_kb & ~mask) * KiB, PAGE_SHIFT, ATTR_PAGE | attr);
 }
 
+void mmu_disable_range_kb(u32 start_kb, u32 size_kb)
+{
+	pte_t *table = mmu_validate_create_sub_table(start_kb, size_kb);
+
+	/* Mask away high address bits that are handled by upper level table. */
+	u32 mask = BLOCK_SIZE/KiB - 1;
+	printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",
+	       start_kb * KiB, (start_kb + size_kb) * KiB);
+	mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
+		       div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
+		       (start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
+}
+
 void mmu_disable_range(u32 start_mb, u32 size_mb)
 {
 	printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",

src/arch/arm/include/armv7/arch/cache.h

@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  * Copyright 2013 Google Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -402,5 +403,6 @@ void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy);
  * Careful: Do NOT map over this address range with mmu_config_range() again
  * later, or you will leak resources and may desync your TLB! */
 void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy);
+void mmu_disable_range_kb(u32 start_kb, u32 size_kb);
 
 #endif /* ARM_CACHE_H */