From e19f40377078375ed85f27e5028ed17d7857d6ca Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 10 Nov 2022 09:46:17 +0100 Subject: [PATCH] mb/siemens/mc_ehl2: Enable Marvell PHY interrupt On this mainboard Marvell PHY INTn is routed to LED[2] pin. Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434 Reviewed-by: Werner Zeh Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index b8ea1b6213..8090927661 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -189,6 +189,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 0 on # PHY address ops m88e1512_ops end @@ -202,6 +204,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 1 on # PHY address ops m88e1512_ops end @@ -218,6 +222,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 1 on # PHY address ops m88e1512_ops end