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vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02

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The headers added are generated as per FSP v2081_02.
Previous FSP version was v2037.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h

BUG=b:180758116
BRANCH=None
TEST=Build and boot ADLRVP

Cq-Depend: chrome-internal:3669105
Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2021-03-04 18:09:44 +05:30 committed by Tim Wawrzynczak
parent 1add483819
commit e1a27f2e49
2 changed files with 331 additions and 314 deletions
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312
src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
View file

@ -216,82 +216,84 @@ typedef struct {
/** Offset 0x0129 - Reserved
**/
UINT8 Reserved1;
UINT8 Reserved1[75];
/** Offset 0x012A - MRC Fast Boot
/** Offset 0x0174 - MRC Fast Boot
Enables/Disable the MRC fast path thru the MRC
$EN_DIS
**/
UINT8 MrcFastBoot;
/** Offset 0x012B - Rank Margin Tool per Task
/** Offset 0x0175 - Rank Margin Tool per Task
This option enables the user to execute Rank Margin Tool per major training step
in the MRC.
$EN_DIS
**/
UINT8 RmtPerTask;
/** Offset 0x012C - Reserved
/** Offset 0x0176 - Reserved
**/
UINT8 Reserved2[4];
UINT8 Reserved2[2];
/** Offset 0x0130 - Tseg Size
/** Offset 0x0178 - Tseg Size
Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
0x0400000:4MB, 0x01000000:16MB
**/
UINT32 TsegSize;
/** Offset 0x0134 - Reserved
/** Offset 0x017C - Reserved
**/
UINT8 Reserved3[3];
/** Offset 0x0137 - Enable SMBus
/** Offset 0x017F - Enable SMBus
Enable/disable SMBus controller.
$EN_DIS
**/
UINT8 SmbusEnable;
/** Offset 0x0138 - Spd Address Tabl
/** Offset 0x0180 - Spd Address Tabl
Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
if SPD Address is 00
**/
UINT8 SpdAddressTable[16];
/** Offset 0x0148 - Platform Debug Consent
/** Offset 0x0190 - Platform Debug Consent
Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks
s0ix\n
Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix
is viable\n
\n
Enabled(Low Power) does not suppoert DCI OOB 4-wire and Tracehub is powergated
by default, s0ix is viable\n
\n
Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users
0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual
**/
UINT8 PlatformDebugConsent;
/** Offset 0x0149 - Reserved
/** Offset 0x0191 - Reserved
**/
UINT8 Reserved4[14];
/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
/** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1=Enable/Set
$EN_DIS
**/
UINT8 X2ApicOptOut;
/** Offset 0x0158 - Reserved
/** Offset 0x01A0 - Reserved
**/
UINT8 Reserved5[40];
/** Offset 0x0180 - Disable VT-d
/** Offset 0x01C8 - Disable VT-d
0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
$EN_DIS
**/
UINT8 VtdDisable;
/** Offset 0x0181 - Reserved
/** Offset 0x01C9 - Reserved
**/
UINT8 Reserved6[4];
/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
/** Offset 0x01CD - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics.
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
@ -299,260 +301,260 @@ typedef struct {
**/
UINT8 IgdDvmt50PreAlloc;
/** Offset 0x0186 - Internal Graphics
/** Offset 0x01CE - Internal Graphics
Enable/disable internal graphics.
$EN_DIS
**/
UINT8 InternalGfx;
/** Offset 0x0187 - Reserved
/** Offset 0x01CF - Reserved
**/
UINT8 Reserved7;
/** Offset 0x0188 - Board Type
/** Offset 0x01D0 - Board Type
MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
Halo, 7=UP Server
0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
**/
UINT8 UserBd;
/** Offset 0x0189 - Reserved
/** Offset 0x01D1 - Reserved
**/
UINT8 Reserved8[3];
/** Offset 0x018C - SA GV
/** Offset 0x01D4 - SA GV
System Agent dynamic frequency support and when enabled memory will be training
at three different frequencies.
0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
**/
UINT8 SaGv;
/** Offset 0x018D - Reserved
/** Offset 0x01D5 - Reserved
**/
UINT8 Reserved9[2];
/** Offset 0x018F - Rank Margin Tool
/** Offset 0x01D7 - Rank Margin Tool
Enable/disable Rank Margin Tool.
$EN_DIS
**/
UINT8 RMT;
/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control
/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control
Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc0Ch0;
/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control
/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control
Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc0Ch1;
/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control
/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control
Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc0Ch2;
/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control
/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control
Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc0Ch3;
/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control
/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control
Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc1Ch0;
/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control
/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control
Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc1Ch1;
/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control
/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control
Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc1Ch2;
/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control
/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control
Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmMc1Ch3;
/** Offset 0x0198 - Reserved
/** Offset 0x01E0 - Reserved
**/
UINT8 Reserved10[2];
/** Offset 0x019A - Memory Reference Clock
/** Offset 0x01E2 - Memory Reference Clock
100MHz, 133MHz.
0:133MHz, 1:100MHz
**/
UINT8 RefClk;
/** Offset 0x019B - Reserved
/** Offset 0x01E3 - Reserved
**/
UINT8 Reserved11[22];
/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
/** Offset 0x01F9 - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
$EN_DIS
**/
UINT8 PchHdaEnable;
/** Offset 0x01B2 - Enable PCH ISH Controller
/** Offset 0x01FA - Enable PCH ISH Controller
0: Disable, 1: Enable (Default) ISH Controller
$EN_DIS
**/
UINT8 PchIshEnable;
/** Offset 0x01B3 - Reserved
/** Offset 0x01FB - Reserved
**/
UINT8 Reserved12[107];
/** Offset 0x021E - IMGU CLKOUT Configuration
/** Offset 0x0266 - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
$EN_DIS
**/
UINT8 ImguClkOutEn[6];
/** Offset 0x0224 - Enable PCIE RP Mask
/** Offset 0x026C - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 CpuPcieRpEnableMask;
/** Offset 0x0228 - Reserved
/** Offset 0x0270 - Reserved
**/
UINT8 Reserved13;
/** Offset 0x0229 - RpClockReqMsgEnable
/** Offset 0x0271 - RpClockReqMsgEnable
**/
UINT8 RpClockReqMsgEnable[3];
/** Offset 0x022C - RpPcieThresholdBytes
/** Offset 0x0274 - RpPcieThresholdBytes
**/
UINT8 RpPcieThresholdBytes[4];
/** Offset 0x0230 - Reserved
/** Offset 0x0278 - Reserved
**/
UINT8 Reserved14;
/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device
/** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortAConfig;
/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device
/** Offset 0x027A - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortBConfig;
/** Offset 0x0233 - Enable or disable HPD of DDI port A
/** Offset 0x027B - Enable or disable HPD of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortAHpd;
/** Offset 0x0234 - Enable or disable HPD of DDI port B
/** Offset 0x027C - Enable or disable HPD of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBHpd;
/** Offset 0x0235 - Enable or disable HPD of DDI port C
/** Offset 0x027D - Enable or disable HPD of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCHpd;
/** Offset 0x0236 - Enable or disable HPD of DDI port 1
/** Offset 0x027E - Enable or disable HPD of DDI port 1
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPort1Hpd;
/** Offset 0x0237 - Enable or disable HPD of DDI port 2
/** Offset 0x027F - Enable or disable HPD of DDI port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Hpd;
/** Offset 0x0238 - Enable or disable HPD of DDI port 3
/** Offset 0x0280 - Enable or disable HPD of DDI port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Hpd;
/** Offset 0x0239 - Enable or disable HPD of DDI port 4
/** Offset 0x0281 - Enable or disable HPD of DDI port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Hpd;
/** Offset 0x023A - Enable or disable DDC of DDI port A
/** Offset 0x0282 - Enable or disable DDC of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortADdc;
/** Offset 0x023B - Enable or disable DDC of DDI port B
/** Offset 0x0283 - Enable or disable DDC of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBDdc;
/** Offset 0x023C - Enable or disable DDC of DDI port C
/** Offset 0x0284 - Enable or disable DDC of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCDdc;
/** Offset 0x023D - Enable DDC setting of DDI Port 1
/** Offset 0x0285 - Enable DDC setting of DDI Port 1
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort1Ddc;
/** Offset 0x023E - Enable DDC setting of DDI Port 2
/** Offset 0x0286 - Enable DDC setting of DDI Port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Ddc;
/** Offset 0x023F - Enable DDC setting of DDI Port 3
/** Offset 0x0287 - Enable DDC setting of DDI Port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Ddc;
/** Offset 0x0240 - Enable DDC setting of DDI Port 4
/** Offset 0x0288 - Enable DDC setting of DDI Port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Ddc;
/** Offset 0x0241 - Reserved
/** Offset 0x0289 - Reserved
**/
UINT8 Reserved15[141];
/** Offset 0x02CE - DMI Gen3 Root port preset values per lane
/** Offset 0x0316 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[8];
/** Offset 0x02D6 - Reserved
/** Offset 0x031E - Reserved
**/
UINT8 Reserved16[150];
/** Offset 0x036C - C6DRAM power gating feature
/** Offset 0x03B4 - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
@ -560,331 +562,331 @@ typedef struct {
**/
UINT8 EnableC6Dram;
/** Offset 0x036D - Reserved
/** Offset 0x03B5 - Reserved
**/
UINT8 Reserved17[5];
/** Offset 0x0372 - Hyper Threading Enable/Disable
/** Offset 0x03BA - Hyper Threading Enable/Disable
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 HyperThreading;
/** Offset 0x0373 - Reserved
/** Offset 0x03BB - Reserved
**/
UINT8 Reserved18;
/** Offset 0x0374 - CPU ratio value
/** Offset 0x03BC - CPU ratio value
CPU ratio value. Valid Range 0 to 63
**/
UINT8 CpuRatio;
/** Offset 0x0375 - Boot frequency
/** Offset 0x03BD - Boot frequency
Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.
1: Maximum non-turbo performance. <b>2: Turbo performance </b>
0:0, 1:1, 2:2
**/
UINT8 BootFrequency;
/** Offset 0x0376 - Reserved
/** Offset 0x03BE - Reserved
**/
UINT8 Reserved19;
/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting
/** Offset 0x03BF - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
/** Offset 0x0378 - Reserved
/** Offset 0x03C0 - Reserved
**/
UINT8 Reserved20;
/** Offset 0x0379 - Enable or Disable VMX
/** Offset 0x03C1 - Enable or Disable VMX
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 VmxEnable;
/** Offset 0x037A - Reserved
/** Offset 0x03C2 - Reserved
**/
UINT8 Reserved21[20];
/** Offset 0x038E - Enable or Disable TME
/** Offset 0x03D6 - Enable or Disable TME
Enable or Disable TME; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TmeEnable;
/** Offset 0x038F - Reserved
/** Offset 0x03D7 - Reserved
**/
UINT8 Reserved22[3];
/** Offset 0x0392 - BiosGuard
/** Offset 0x03DA - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
/** Offset 0x0393
/** Offset 0x03DB
**/
UINT8 BiosGuardToolsInterface;
/** Offset 0x0394 - Reserved
/** Offset 0x03DC - Reserved
**/
UINT8 Reserved23[4];
/** Offset 0x0398 - PrmrrSize
/** Offset 0x03E0 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
/** Offset 0x039C - SinitMemorySize
/** Offset 0x03E4 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
/** Offset 0x03A0 - Reserved
/** Offset 0x03E8 - Reserved
**/
UINT8 Reserved24[8];
/** Offset 0x03A8 - TxtHeapMemorySize
/** Offset 0x03F0 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
/** Offset 0x03AC - TxtDprMemorySize
/** Offset 0x03F4 - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
/** Offset 0x03B0 - Reserved
/** Offset 0x03F8 - Reserved
**/
UINT8 Reserved25[625];
/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
/** Offset 0x0669 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
/** Offset 0x0622 - Reserved
/** Offset 0x066A - Reserved
**/
UINT8 Reserved26[3];
/** Offset 0x0625 - Usage type for ClkSrc
/** Offset 0x066D - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
/** Offset 0x0637 - Reserved
/** Offset 0x067F - Reserved
**/
UINT8 Reserved27[14];
/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
/** Offset 0x068D - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
/** Offset 0x0657 - Reserved
/** Offset 0x069F - Reserved
**/
UINT8 Reserved28[93];
/** Offset 0x06B4 - Enable PCIE RP Mask
/** Offset 0x06FC - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
/** Offset 0x06B8 - Reserved
/** Offset 0x0700 - Reserved
**/
UINT8 Reserved29[2];
/** Offset 0x06BA - Enable HD Audio Link
/** Offset 0x0702 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
/** Offset 0x06BB - Reserved
/** Offset 0x0703 - Reserved
**/
UINT8 Reserved30[3];
/** Offset 0x06BE - Enable HD Audio DMIC_N Link
/** Offset 0x0706 - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
/** Offset 0x0708 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
/** Offset 0x0710 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
/** Offset 0x06D0 - Enable HD Audio DSP
/** Offset 0x0718 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
/** Offset 0x06D1 - Reserved
/** Offset 0x0719 - Reserved
**/
UINT8 Reserved31[3];
/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
/** Offset 0x071C - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
/** Offset 0x06DC - Enable HD Audio SSP0 Link
/** Offset 0x0724 - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
/** Offset 0x072A - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
/** Offset 0x06E6 - iDisp-Link Frequency
/** Offset 0x072E - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
/** Offset 0x06E7 - iDisp-Link T-mode
/** Offset 0x072F - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
/** Offset 0x06E8 - iDisplay Audio Codec disconnection
/** Offset 0x0730 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
/** Offset 0x06E9 - Debug Interfaces
/** Offset 0x0731 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
/** Offset 0x06EA - Serial Io Uart Debug Controller Number
/** Offset 0x0732 - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
Core interface, it cannot be used for debug purpose.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
/** Offset 0x06EB - Reserved
/** Offset 0x0733 - Reserved
**/
UINT8 Reserved32[13];
/** Offset 0x06F8 - ISA Serial Base selection
/** Offset 0x0740 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
/** Offset 0x06F9 - Reserved
/** Offset 0x0741 - Reserved
**/
UINT8 Reserved33[4];
/** Offset 0x06FD - MRC Safe Config
/** Offset 0x0745 - MRC Safe Config
Enables/Disable MRC Safe Config
$EN_DIS
**/
UINT8 MrcSafeConfig;
/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
/** Offset 0x0746 - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
/** Offset 0x0747 - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
/** Offset 0x0748 - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
/** Offset 0x0749 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
/** Offset 0x074A - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
/** Offset 0x074B - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
/** Offset 0x0704 - TCSS DMA0 Enable
/** Offset 0x074C - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
/** Offset 0x0705 - TCSS DMA1 Enable
/** Offset 0x074D - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
/** Offset 0x0706 - Reserved
/** Offset 0x074E - Reserved
**/
UINT8 Reserved34[2];
/** Offset 0x0708 - Early Command Training
/** Offset 0x0750 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
/** Offset 0x0709 - Reserved
/** Offset 0x0751 - Reserved
**/
UINT8 Reserved35[58];
UINT8 Reserved35[59];
/** Offset 0x0743 - Rank Margin Tool Per Bit
/** Offset 0x078C - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
/** Offset 0x0744 - Reserved
/** Offset 0x078D - Reserved
**/
UINT8 Reserved36[6];
UINT8 Reserved36[5];
/** Offset 0x074A - Ch Hash Mask
/** Offset 0x0792 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
/** Offset 0x074C - Reserved
/** Offset 0x0794 - Reserved
**/
UINT8 Reserved37[66];
/** Offset 0x078E - PcdSerialDebugLevel
/** Offset 0x07D6 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@ -893,98 +895,98 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
/** Offset 0x078F - Reserved
/** Offset 0x07D7 - Reserved
**/
UINT8 Reserved38[2];
/** Offset 0x0791 - Safe Mode Support
/** Offset 0x07D9 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
$EN_DIS
**/
UINT8 SafeMode;
/** Offset 0x0792 - Reserved
/** Offset 0x07DA - Reserved
**/
UINT8 Reserved39[2];
/** Offset 0x0794 - TCSS USB Port Enable
/** Offset 0x07DC - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
/** Offset 0x0795 - Reserved
/** Offset 0x07DD - Reserved
**/
UINT8 Reserved40[3];
/** Offset 0x0798 - RMTLoopCount
/** Offset 0x07E0 - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
/** Offset 0x0799 - Reserved
/** Offset 0x07E1 - Reserved
**/
UINT8 Reserved41[29];
UINT8 Reserved41[31];
/** Offset 0x07B6 - Command Pins Mapping
/** Offset 0x0800 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
/** Offset 0x07B7 - Reserved
/** Offset 0x0801 - Reserved
**/
UINT8 Reserved42[12];
UINT8 Reserved42[10];
/** Offset 0x07C3 - Skip external display device scanning
/** Offset 0x080B - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
/** Offset 0x07C4 - Reserved
/** Offset 0x080C - Reserved
**/
UINT8 Reserved43;
/** Offset 0x07C5 - Lock PCU Thermal Management registers
/** Offset 0x080D - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
/** Offset 0x07C6 - Reserved
/** Offset 0x080E - Reserved
**/
UINT8 Reserved44[131];
/** Offset 0x0849 - Skip CPU replacement check
/** Offset 0x0891 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
/** Offset 0x084A - Reserved
/** Offset 0x0892 - Reserved
**/
UINT8 Reserved45[292];
/** Offset 0x096E - Serial Io Uart Debug Mode
/** Offset 0x09B6 - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
/** Offset 0x096F - Reserved
/** Offset 0x09B7 - Reserved
**/
UINT8 Reserved46[185];
/** Offset 0x0A28 - GPIO Override
/** Offset 0x0A70 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
**/
UINT8 GpioOverride;
/** Offset 0x0A29 - Reserved
/** Offset 0x0A71 - Reserved
**/
UINT8 Reserved47[23];
} FSP_M_CONFIG;
@ -1005,11 +1007,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x0A40
/** Offset 0x0A88
**/
UINT8 UnusedUpdSpace25[6];
UINT8 UnusedUpdSpace23[6];
/** Offset 0x0A46
/** Offset 0x0A8E
**/
UINT16 UpdTerminator;
} FSPM_UPD;

333
src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
View file

@ -160,7 +160,22 @@ typedef struct {
/** Offset 0x00AF - Reserved
**/
UINT8 Reserved4[26];
UINT8 Reserved4;
/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
**/
UINT32 DevIntConfigPtr;
/** Offset 0x00B4 - Number of DevIntConfig Entry
Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
must not be NULL.
**/
UINT8 NumOfDevIntConfig;
/** Offset 0x00B5 - Reserved
**/
UINT8 Reserved5[20];
/** Offset 0x00C9 - Enable SATA
Enable/disable SATA controller.
@ -182,7 +197,7 @@ typedef struct {
/** Offset 0x00D2 - Reserved
**/
UINT8 Reserved5[35];
UINT8 Reserved6[35];
/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW
Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
@ -205,7 +220,7 @@ typedef struct {
/** Offset 0x010A - Reserved
**/
UINT8 Reserved6[65];
UINT8 Reserved7[65];
/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS lines.
@ -214,7 +229,7 @@ typedef struct {
/** Offset 0x0152 - Reserved
**/
UINT8 Reserved7[2];
UINT8 Reserved8[2];
/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@ -250,7 +265,7 @@ typedef struct {
/** Offset 0x01C5 - Reserved
**/
UINT8 Reserved8[7];
UINT8 Reserved9[7];
/** Offset 0x01CC - I2Cn Device Mode
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
@ -272,7 +287,7 @@ typedef struct {
/** Offset 0x0214 - Reserved
**/
UINT8 Reserved9[192];
UINT8 Reserved10[192];
/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
@ -324,7 +339,7 @@ typedef struct {
/** Offset 0x033C - Reserved
**/
UINT8 Reserved10[80];
UINT8 Reserved11[80];
/** Offset 0x038C - Enable LAN
Enable/disable LAN controller.
@ -334,7 +349,7 @@ typedef struct {
/** Offset 0x038D - Reserved
**/
UINT8 Reserved11[11];
UINT8 Reserved12[11];
/** Offset 0x0398 - PCIe PTM enable/disable
Enable/disable Precision Time Measurement for PCIE Root Ports.
@ -343,7 +358,7 @@ typedef struct {
/** Offset 0x03B4 - Reserved
**/
UINT8 Reserved12[81];
UINT8 Reserved13[81];
/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
@ -359,7 +374,7 @@ typedef struct {
/** Offset 0x0407 - Reserved
**/
UINT8 Reserved13;
UINT8 Reserved14;
/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
@ -368,53 +383,53 @@ typedef struct {
/** Offset 0x040A - Reserved
**/
UINT8 Reserved14[50];
UINT8 Reserved15[42];
/** Offset 0x043C - CNVi Configuration
/** Offset 0x0434 - CNVi Configuration
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
0:Disable, 1:Auto
**/
UINT8 CnviMode;
/** Offset 0x043D - Reserved
/** Offset 0x0435 - Reserved
**/
UINT8 Reserved15;
UINT8 Reserved16;
/** Offset 0x043E - CNVi BT Core
/** Offset 0x0436 - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
/** Offset 0x043F - CNVi BT Audio Offload
/** Offset 0x0437 - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
/** Offset 0x0440 - Reserved
/** Offset 0x0438 - Reserved
**/
UINT8 Reserved16[4];
UINT8 Reserved17[4];
/** Offset 0x0444 - CNVi RF_RESET pin muxing
/** Offset 0x043C - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
/** Offset 0x0448 - CNVi CLKREQ pin muxing
/** Offset 0x0440 - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
in GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
/** Offset 0x044C - Reserved
/** Offset 0x0444 - Reserved
**/
UINT8 Reserved17[172];
UINT8 Reserved18[172];
/** Offset 0x04F8 - CdClock Frequency selection
/** Offset 0x04F0 - CdClock Frequency selection
0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
@ -422,318 +437,318 @@ typedef struct {
**/
UINT8 CdClock;
/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
/** Offset 0x04F1 - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
/** Offset 0x04FA - Enable D3 Hot in TCSS
/** Offset 0x04F2 - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
/** Offset 0x04FB - Reserved
/** Offset 0x04F3 - Reserved
**/
UINT8 Reserved18;
UINT8 Reserved19;
/** Offset 0x04FC - TypeC port GPIO setting
/** Offset 0x04F4 - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
= AlderLake)
**/
UINT32 IomTypeCPortPadCfg[8];
/** Offset 0x051C - Reserved
/** Offset 0x0514 - Reserved
**/
UINT8 Reserved19[8];
UINT8 Reserved20[8];
/** Offset 0x0524 - Enable D3 Cold in TCSS
/** Offset 0x051C - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
/** Offset 0x0525 - Reserved
/** Offset 0x051D - Reserved
**/
UINT8 Reserved20[3];
UINT8 Reserved21[3];
/** Offset 0x0528 - Intel Graphics VBT (Video BIOS Table) Size
/** Offset 0x0520 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
**/
UINT32 VbtSize;
/** Offset 0x052C - Platform LID Status for LFP Displays.
/** Offset 0x0524 - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
/** Offset 0x052D - Reserved
/** Offset 0x0525 - Reserved
**/
UINT8 Reserved21[8];
UINT8 Reserved22[8];
/** Offset 0x0535 - Enable VMD controller
/** Offset 0x052D - Enable VMD controller
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdEnable;
/** Offset 0x0536 - Reserved
/** Offset 0x052E - Reserved
**/
UINT8 Reserved22[120];
UINT8 Reserved23[120];
/** Offset 0x05AE - TCSS Aux Orientation Override Enable
/** Offset 0x05A6 - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
/** Offset 0x05A8 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
/** Offset 0x05B2 - Reserved
/** Offset 0x05AA - Reserved
**/
UINT8 Reserved23;
UINT8 Reserved24;
/** Offset 0x05B3 - ITBT Root Port Enable
/** Offset 0x05AB - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
/** Offset 0x05B7 - Reserved
/** Offset 0x05AF - Reserved
**/
UINT8 Reserved24[3];
UINT8 Reserved25[3];
/** Offset 0x05BA - ITbtConnectTopology Timeout value
/** Offset 0x05B2 - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
/** Offset 0x05BC - Reserved
/** Offset 0x05B4 - Reserved
**/
UINT8 Reserved25[7];
UINT8 Reserved26[7];
/** Offset 0x05C3 - Enable/Disable PTM
/** Offset 0x05BB - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
/** Offset 0x05C7 - Reserved
/** Offset 0x05BF - Reserved
**/
UINT8 Reserved26[200];
UINT8 Reserved27[200];
/** Offset 0x068F - Skip Multi-Processor Initialization
/** Offset 0x0687 - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. </b>0: Initialize; <b>1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
/** Offset 0x0690 - Reserved
/** Offset 0x0688 - Reserved
**/
UINT8 Reserved27[8];
UINT8 Reserved28[8];
/** Offset 0x0698 - CpuMpPpi
/** Offset 0x0690 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
/** Offset 0x069C - Reserved
/** Offset 0x0694 - Reserved
**/
UINT8 Reserved28[70];
UINT8 Reserved29[60];
/** Offset 0x06E2 - Enable Power Optimizer
/** Offset 0x06D0 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
/** Offset 0x06E3 - Reserved
/** Offset 0x06D1 - Reserved
**/
UINT8 Reserved29[33];
UINT8 Reserved30[33];
/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
/** Offset 0x06F2 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
/** Offset 0x0705 - Reserved
/** Offset 0x06F3 - Reserved
**/
UINT8 Reserved30[2];
UINT8 Reserved31[2];
/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
/** Offset 0x06F5 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
/** Offset 0x0708 - Enable PCH ISH UART pins assigned
/** Offset 0x06F6 - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
/** Offset 0x070A - Enable PCH ISH I2C pins assigned
/** Offset 0x06F8 - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
/** Offset 0x070D - Enable PCH ISH GP pins assigned
/** Offset 0x06FB - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[8];
/** Offset 0x0715 - Reserved
/** Offset 0x0703 - Reserved
**/
UINT8 Reserved31[2];
UINT8 Reserved32[2];
/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
/** Offset 0x0705 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
/** Offset 0x0718 - Reserved
/** Offset 0x0706 - Reserved
**/
UINT8 Reserved32[2];
UINT8 Reserved33[2];
/** Offset 0x071A - RTC Cmos Memory Lock
/** Offset 0x0708 - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
/** Offset 0x071B - Enable PCIE RP HotPlug
/** Offset 0x0709 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[28];
/** Offset 0x0737 - Reserved
/** Offset 0x0725 - Reserved
**/
UINT8 Reserved33[56];
UINT8 Reserved34[56];
/** Offset 0x076F - Enable PCIE RP Clk Req Detect
/** Offset 0x075D - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[28];
/** Offset 0x078B - PCIE RP Advanced Error Report
/** Offset 0x0779 - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[28];
/** Offset 0x07A7 - Reserved
/** Offset 0x0795 - Reserved
**/
UINT8 Reserved34[196];
UINT8 Reserved35[196];
/** Offset 0x086B - PCIE RP Max Payload
/** Offset 0x0859 - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[28];
/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
/** Offset 0x0875 - Touch Host Controller Port 0 Assignment
Assign THC Port 0
0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
**/
UINT8 ThcPort0Assignment;
/** Offset 0x0888 - Reserved
/** Offset 0x0876 - Reserved
**/
UINT8 Reserved35[5];
UINT8 Reserved36[7];
/** Offset 0x088D - Touch Host Controller Port 1 Assignment
/** Offset 0x087D - Touch Host Controller Port 1 Assignment
Assign THC Port 1
0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
**/
UINT8 ThcPort1Assignment;
/** Offset 0x088E - Reserved
/** Offset 0x087E - Reserved
**/
UINT8 Reserved36[91];
UINT8 Reserved37[91];
/** Offset 0x08E9 - PCIE RP Aspm
/** Offset 0x08D9 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[28];
/** Offset 0x0905 - PCIE RP L1 Substates
/** Offset 0x08F5 - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[28];
/** Offset 0x0921 - Reserved
/** Offset 0x0911 - Reserved
**/
UINT8 Reserved37[28];
UINT8 Reserved38[28];
/** Offset 0x093D - PCIE RP Ltr Enable
/** Offset 0x092D - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[28];
/** Offset 0x0959 - Reserved
/** Offset 0x0949 - Reserved
**/
UINT8 Reserved38[104];
UINT8 Reserved39[104];
/** Offset 0x09C1 - PCIE Compliance Test Mode
/** Offset 0x09B1 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
/** Offset 0x09C2 - Reserved
/** Offset 0x09B2 - Reserved
**/
UINT8 Reserved39[27];
UINT8 Reserved40[27];
/** Offset 0x09DD - PCH Sata Pwr Opt Enable
/** Offset 0x09CD - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
/** Offset 0x09DE - Reserved
/** Offset 0x09CE - Reserved
**/
UINT8 Reserved40[50];
UINT8 Reserved41[50];
/** Offset 0x0A10 - Enable SATA Port DmVal
/** Offset 0x0A00 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
/** Offset 0x0A18 - Enable SATA Port DmVal
/** Offset 0x0A08 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
/** Offset 0x0A28 - Reserved
/** Offset 0x0A18 - Reserved
**/
UINT8 Reserved41[62];
UINT8 Reserved42[62];
/** Offset 0x0A66 - USB2 Port Over Current Pin
/** Offset 0x0A56 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
/** Offset 0x0A76 - USB3 Port Over Current Pin
/** Offset 0x0A66 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
/** Offset 0x0A80 - Reserved
/** Offset 0x0A70 - Reserved
**/
UINT8 Reserved42[16];
UINT8 Reserved43[16];
/** Offset 0x0A90 - Enable 8254 Static Clock Gating
/** Offset 0x0A80 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@ -741,7 +756,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
/** Offset 0x0A81 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@ -749,22 +764,22 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
/** Offset 0x0A92 - Reserved
/** Offset 0x0A82 - Reserved
**/
UINT8 Reserved43;
UINT8 Reserved44;
/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
/** Offset 0x0A83 - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
/** Offset 0x0A94 - Reserved
/** Offset 0x0A84 - Reserved
**/
UINT8 Reserved44[93];
UINT8 Reserved45[93];
/** Offset 0x0AF1 - Enable PS_ON.
/** Offset 0x0AE1 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@ -772,39 +787,39 @@ typedef struct {
**/
UINT8 PsOnEnable;
/** Offset 0x0AF2 - Reserved
/** Offset 0x0AE2 - Reserved
**/
UINT8 Reserved45[211];
UINT8 Reserved46[211];
/** Offset 0x0BC5 - PCIE Compliance Test Mode
/** Offset 0x0BB5 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 CpuPcieComplianceTestMode;
/** Offset 0x0BC6 - Reserved
/** Offset 0x0BB6 - Reserved
**/
UINT8 Reserved46[106];
UINT8 Reserved47[106];
/** Offset 0x0C30 - RpPtmBytes
/** Offset 0x0C20 - RpPtmBytes
**/
UINT8 RpPtmBytes[4];
/** Offset 0x0C34 - Reserved
/** Offset 0x0C24 - Reserved
**/
UINT8 Reserved47[95];
UINT8 Reserved48[95];
/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
/** Offset 0x0C83 - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
/** Offset 0x0C94 - Reserved
/** Offset 0x0C84 - Reserved
**/
UINT8 Reserved48;
UINT8 Reserved49;
/** Offset 0x0C95 - GT Frequency Limit
/** Offset 0x0C85 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@ -818,22 +833,22 @@ typedef struct {
**/
UINT8 GtFreqMax;
/** Offset 0x0C96 - Reserved
/** Offset 0x0C86 - Reserved
**/
UINT8 Reserved49[24];
UINT8 Reserved50[24];
/** Offset 0x0CAE - Enable or Disable HWP
/** Offset 0x0C9E - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2-3:Reserved
$EN_DIS
**/
UINT8 Hwp;
/** Offset 0x0CAF - Reserved
/** Offset 0x0C9F - Reserved
**/
UINT8 Reserved50[8];
UINT8 Reserved51[8];
/** Offset 0x0CB7 - TCC Activation Offset
/** Offset 0x0CA7 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
@ -841,73 +856,73 @@ typedef struct {
**/
UINT8 TccActivationOffset;
/** Offset 0x0CB8 - Reserved
/** Offset 0x0CA8 - Reserved
**/
UINT8 Reserved51[34];
UINT8 Reserved52[34];
/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
/** Offset 0x0CCA - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
/** Offset 0x0CDB - Reserved
/** Offset 0x0CCB - Reserved
**/
UINT8 Reserved52[157];
UINT8 Reserved53[157];
/** Offset 0x0D78 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
/** Offset 0x0D68 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 EnableFastMsrHwpReq;
/** Offset 0x0D79 - Reserved
/** Offset 0x0D69 - Reserved
**/
UINT8 Reserved53[38];
UINT8 Reserved54[38];
/** Offset 0x0D9F - Enable LOCKDOWN SMI
/** Offset 0x0D8F - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
/** Offset 0x0D90 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
/** Offset 0x0DA1 - Unlock all GPIO pads
/** Offset 0x0D91 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
/** Offset 0x0DA2 - Reserved
/** Offset 0x0D92 - Reserved
**/
UINT8 Reserved54[2];
UINT8 Reserved55[2];
/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
/** Offset 0x0D94 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[28];
/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
/** Offset 0x0DCC - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[28];
/** Offset 0x0E14 - Reserved
/** Offset 0x0E04 - Reserved
**/
UINT8 Reserved55[313];
UINT8 Reserved56[313];
/** Offset 0x0F4D - LpmStateEnableMask
/** Offset 0x0F3D - LpmStateEnableMask
**/
UINT8 LpmStateEnableMask;
/** Offset 0x0F4E - Reserved
/** Offset 0x0F3E - Reserved
**/
UINT8 Reserved56[122];
UINT8 Reserved57[122];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@ -926,11 +941,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
/** Offset 0x0FC8
/** Offset 0x0FB8
**/
UINT8 UnusedUpdSpace43[6];
UINT8 UnusedUpdSpace44[6];
/** Offset 0x0FCE
/** Offset 0x0FBE
**/
UINT16 UpdTerminator;
} FSPS_UPD;