GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/i82801ix: Use pmutil.h definitions 

Also drop now-redundant definitions and include headers where needed.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-21 17:02:43 +02:00
parent b60aeca26c
commit e1a616cf99
4 changed files with 3 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/northbridge/intel/gm45/romstage.c
View File

@ -11,6 +11,7 @@
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <southbridge/intel/common/pmutil.h>
#include <string.h> #include <string.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)

1
src/southbridge/intel/i82801ix/early_init.c
View File

@ -3,6 +3,7 @@
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include <southbridge/intel/common/pmutil.h>
#include "i82801ix.h" #include "i82801ix.h"
#include "chip.h" #include "chip.h"

33
src/southbridge/intel/i82801ix/i82801ix.h
View File

@ -23,30 +23,6 @@
#define APM_CNT 0xb2 #define APM_CNT 0xb2
#define PM1_STS 0x00
#define PWRBTN_STS (1 << 8)
#define RTC_STS (1 << 10)
#define PM1_EN 0x02
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define PM1_CNT 0x04
#define SCI_EN (1 << 0)
#define PM_LV2 0x14
#define PM_LV3 0x15
#define PM_LV4 0x16
#define PM_LV5 0x17
#define PM_LV6 0x18
#define GPE0_STS 0x20
#define SMI_EN 0x30
#define PERIODIC_EN (1 << 14)
#define TCO_EN (1 << 13)
#define APMC_EN (1 << 5)
#define BIOS_EN (1 << 2)
#define EOS (1 << 1)
#define GBL_SMI_EN (1 << 0)
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
#define GP_IO_USE_SEL 0x00 #define GP_IO_USE_SEL 0x00
@ -65,7 +41,6 @@
#define MAINBOARD_POWER_KEEP 2 #define MAINBOARD_POWER_KEEP 2
/* D31:F0 LPC bridge */ /* D31:F0 LPC bridge */
#define D31F0_PMBASE 0x40
#define D31F0_ACPI_CNTL 0x44 #define D31F0_ACPI_CNTL 0x44
#define D31F0_GPIO_BASE 0x48 #define D31F0_GPIO_BASE 0x48
#define D31F0_GPIO_CNTL 0x4c #define D31F0_GPIO_CNTL 0x4c
@ -84,17 +59,9 @@
#define D31F0_GEN2_DEC 0x88 #define D31F0_GEN2_DEC 0x88
#define D31F0_GEN3_DEC 0x8c #define D31F0_GEN3_DEC 0x8c
#define D31F0_GEN4_DEC 0x90 #define D31F0_GEN4_DEC 0x90
#define D31F0_GEN_PMCON_1 0xa0
#define D31F0_GEN_PMCON_3 0xa4
#define D31F0_C5_EXIT_TIMING 0xa8 #define D31F0_C5_EXIT_TIMING 0xa8
#define D31F0_CxSTATE_CNF 0xa9 #define D31F0_CxSTATE_CNF 0xa9
#define D31F0_C4TIMING_CNT 0xaa #define D31F0_C4TIMING_CNT 0xaa
#define D31F0_GPIO_ROUT 0xb8
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
#define RTC_POWER_FAILED (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
/* D31:F2 SATA */ /* D31:F2 SATA */

1
src/southbridge/intel/i82801ix/lpc.c
View File

@ -20,6 +20,7 @@
#include "i82801ix.h" #include "i82801ix.h"
#include "nvs.h" #include "nvs.h"
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#define NMI_OFF 0 #define NMI_OFF 0