diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb
index a650552915..42bdade09f 100644
--- a/src/mainboard/asus/p2b/devicetree.cb
+++ b/src/mainboard/asus/p2b/devicetree.cb
@@ -42,14 +42,14 @@ chip northbridge/intel/i440bx		# Northbridge
       device pci 4.1 on	end		# IDE
       device pci 4.2 on	end		# USB
       device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
+      register "ide0_enable" = "true"
+      register "ide1_enable" = "true"
+      register "ide_legacy_enable" = "true"
       # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
+      register "ide0_drive0_udma33_enable" = "true"
+      register "ide0_drive1_udma33_enable" = "true"
+      register "ide1_drive0_udma33_enable" = "true"
+      register "ide1_drive1_udma33_enable" = "true"
       register "thrm_polarity" = "1"
       register "lid_polarity" = "1"
     end
diff --git a/src/mainboard/emulation/qemu-i440fx/devicetree.cb b/src/mainboard/emulation/qemu-i440fx/devicetree.cb
index 385fa247b2..cecba1c82a 100644
--- a/src/mainboard/emulation/qemu-i440fx/devicetree.cb
+++ b/src/mainboard/emulation/qemu-i440fx/devicetree.cb
@@ -6,8 +6,8 @@ chip mainboard/emulation/qemu-i440fx
 			device pci 01.0 on end	# ISA bridge
 			device pci 01.1 on end	# IDE
 			device pci 01.3 on end	# ACPI
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
+			register "ide0_enable" = "true"
+			register "ide1_enable" = "true"
 			register "gpo" = "0x7fffbbff"
 		end
 	end
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 264f74fa70..5652cd2a39 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -4,17 +4,18 @@
 #define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
 
 #include <device/device.h>
+#include <types.h>
 
 struct southbridge_intel_i82371eb_config {
-	int ide0_enable:1;
-	int ide0_drive0_udma33_enable:1;
-	int ide0_drive1_udma33_enable:1;
-	int ide1_enable:1;
-	int ide1_drive0_udma33_enable:1;
-	int ide1_drive1_udma33_enable:1;
-	int ide_legacy_enable:1;
-	int usb_enable:1;
-	int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */
+	bool ide0_enable;
+	bool ide0_drive0_udma33_enable;
+	bool ide0_drive1_udma33_enable;
+	bool ide1_enable;
+	bool ide1_drive0_udma33_enable;
+	bool ide1_drive1_udma33_enable;
+	bool ide_legacy_enable;
+	bool usb_enable;
+	bool gpo22_enable; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */
 	int gpo22:1;
 	int gpo23:1;
 	/* acpi */