soc/intel/cnl: Add new Kconfig option which matches its FSPs name

Since there are 4 different versions of FSPs for the Comet Lake
platform, add a new Kconfig option for the currently used SoC being able
to differ between the various SoCs and FSPs.

The new Kconfig option selects the Comet Lake SoC as base for taking
over its specific configuration and is only used for configuring the
path to its specific FSP header files and FSP binary.

Also, adjust all related mainboards so that their Kconfig selects the
new option.

For details, please see
https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg

Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch
and both images are equal.

Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-08-31 19:51:52 +00:00 committed by Michael Niewöhner
parent 49f0a40da5
commit e1af5b8d26
5 changed files with 10 additions and 6 deletions

View File

@ -16,7 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
select SYSTEM_TYPE_LAPTOP

View File

@ -39,7 +39,7 @@ config BOARD_GOOGLE_HATCH_COMMON
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_DTT
if BOARD_GOOGLE_HATCH_COMMON

View File

@ -14,4 +14,4 @@ config BOARD_INTEL_COFFEELAKE_RVP8
select SOC_INTEL_COFFEELAKE
config BOARD_INTEL_COMETLAKE_RVPU
bool "-> Cometlake U DDR4 RVP"
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMETLAKE_1

View File

@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD

View File

@ -47,6 +47,10 @@ config SOC_INTEL_COMETLAKE
help
Intel Cometlake support
config SOC_INTEL_COMETLAKE_1
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_CANNONLAKE_PCH_H
bool
help
@ -313,12 +317,12 @@ endchoice
config FSP_HEADER_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
config FSP_FD_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE_1
config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
int "Debug Consent for CNL"