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amd/stoneyridge: Fix PmControl register size in SMI handler 

The AMD implementation of this register is only 16 bits.  Change the
source accordingly.

TEST=Suspend/Resume a Grunt several times

Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson 2018-10-07 21:45:47 -06:00 committed by Martin Roth
parent edba21e4a6
commit e1b1ec7154
1 changed files with 5 additions and 5 deletions
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10
src/soc/amd/stoneyridge/smihandler.c
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@ -122,13 +122,13 @@ static void disable_all_smi_status(void)
static void sb_slp_typ_handler(void)
{
uint32_t pm1cnt, pci_ctrl, reg32;
uint16_t reg16;
uint32_t pci_ctrl, reg32;
uint16_t pm1cnt, reg16;
uint8_t slp_typ, rst_ctrl;
/* Figure out SLP_TYP */
pm1cnt = inl(pm_acpi_pm_cnt_blk());
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", pm1cnt);
pm1cnt = inw(pm_acpi_pm_cnt_blk());
printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt);
slp_typ = acpi_sleep_from_pm1(pm1cnt);
/* Do any mainboard sleep handling */
@ -196,7 +196,7 @@ static void sb_slp_typ_handler(void)
} /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */
/* Reissue Pm1 write */
outl(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk());
outw(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk());
hlt();
}
}