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soc/intel/cannonlake: Update GPIO ASL 

GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.

BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.

Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2018-02-08 16:58:47 -08:00 committed by Aaron Durbin
parent 20123a8838
commit e1b8221498
1 changed files with 32 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
src/soc/intel/cannonlake/acpi/gpio.asl
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@ -28,6 +28,8 @@ Device (GPIO)
{ {
Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM0)
Memory32Fixed (ReadWrite, 0, 0, COM1) Memory32Fixed (ReadWrite, 0, 0, COM1)
Memory32Fixed (ReadWrite, 0, 0, COM2)
Memory32Fixed (ReadWrite, 0, 0, COM3)
Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM4)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 } { GPIO_IRQ14 }
@ -47,11 +49,24 @@ Device (GPIO)
Store (^^PCRB (PID_GPIOCOM1), BAS1) Store (^^PCRB (PID_GPIOCOM1), BAS1)
Store (GPIO_BASE_SIZE, LEN1) Store (GPIO_BASE_SIZE, LEN1)
/* GPIO Community 2 */
CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
Store (^^PCRB (PID_GPIOCOM2), BAS2)
Store (GPIO_BASE_SIZE, LEN2)
/* GPIO Community 3 */
CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
Store (^^PCRB (PID_GPIOCOM3), BAS3)
Store (GPIO_BASE_SIZE, LEN3)
/* GPIO Community 4 */ /* GPIO Community 4 */
CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
CreateDWordField (^RBUF, ^COM4._LEN, LEN3) CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
Store (^^PCRB (PID_GPIOCOM4), BAS4) Store (^^PCRB (PID_GPIOCOM4), BAS4)
Store (GPIO_BASE_SIZE, LEN3) Store (GPIO_BASE_SIZE, LEN4)
Return (RBUF) Return (RBUF)
} }
@ -69,19 +84,31 @@ Device (GPIO)
Method (GADD, 1, NotSerialized) Method (GADD, 1, NotSerialized)
{ {
/* GPIO Community 0 */ /* GPIO Community 0 */
If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_G7))) If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))
{ {
Store (PID_GPIOCOM0, Local0) Store (PID_GPIOCOM0, Local0)
Subtract (Arg0, GPP_A0, Local1) Subtract (Arg0, GPP_A0, Local1)
} }
/* GPIO Community 1 */ /* GPIO Community 1 */
If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPP_H23))) If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))
{ {
Store (PID_GPIOCOM1, Local0) Store (PID_GPIOCOM1, Local0)
Subtract (Arg0, GPP_D0, Local1) Subtract (Arg0, GPP_D0, Local1)
} }
/* GPIO Community 2 */
If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11)))
{
Store (PID_GPIOCOM1, Local0)
Subtract (Arg0, GPD0, Local1)
}
/* GPIO Community 3 */
If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))
{
Store (PID_GPIOCOM1, Local0)
Subtract (Arg0, HDA_BCLK, Local1)
}
/* GPIO Community 04*/ /* GPIO Community 04*/
If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))
{ {
Store (PID_GPIOCOM4, Local0) Store (PID_GPIOCOM4, Local0)
Subtract (Arg0, GPP_C0, Local1) Subtract (Arg0, GPP_C0, Local1)