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amd/stoneyridge: Create an MCA structure 

Convert the Machine Check reporting to use a newly defined structure.
This will facilitate later patches that will pass pointers to the MSR
values.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28476
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2018-09-04 13:15:11 -06:00 committed by Martin Roth
parent 0b4a1e220a
commit e1bd38bec5
1 changed files with 26 additions and 17 deletions
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43
src/soc/amd/stoneyridge/mca.c
View File

@ -20,6 +20,14 @@
#include <soc/northbridge.h>
#include <console/console.h>
struct mca_bank {
msr_t ctl;
msr_t sts;
msr_t addr;
msr_t misc;
msr_t cmask;
};
static const char *const mca_bank_name[] = {
"Load-store unit",
"Instruction fetch unit",
@ -33,45 +41,46 @@ static const char *const mca_bank_name[] = {
void check_mca(void)
{
int i;
msr_t msr;
msr_t cap;
struct mca_bank mci;
int num_banks;
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
cap = rdmsr(MCG_CAP);
num_banks = cap.lo & MCA_BANKS_MASK;
if (is_warm_reset()) {
for (i = 0 ; i < num_banks ; i++) {
if (i == 3) /* Reserved in Family 15h */
continue;
msr = rdmsr(MC0_STATUS + (i * 4));
if (msr.hi || msr.lo) {
mci.sts = rdmsr(MC0_STATUS + (i * 4));
if (mci.sts.hi || mci.sts.lo) {
int core = cpuid_ebx(1) >> 24;
printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",
core, i, mca_bank_name[i]);
printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MC0_ADDR + (i * 4));
i, mci.sts.hi, mci.sts.lo);
mci.addr = rdmsr(MC0_ADDR + (i * 4));
printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MC0_MISC + (i * 4));
i, mci.addr.hi, mci.addr.lo);
mci.misc = rdmsr(MC0_MISC + (i * 4));
printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL + (i * 4));
i, mci.misc.hi, mci.misc.lo);
mci.ctl = rdmsr(MC0_CTL + (i * 4));
printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + i);
i, mci.ctl.hi, mci.ctl.lo);
mci.cmask = rdmsr(MC0_CTL_MASK + i);
printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",
i, msr.hi, msr.lo);
i, mci.cmask.hi, mci.cmask.lo);
}
}
}
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
mci.sts.lo = 0;
mci.sts.hi = 0;
for (i = 0 ; i < num_banks ; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(MC0_STATUS + (i * 4), mci.sts);
}