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mainboard/intel/cannonlake_rvp: Include ChromeOS support 

Add ChromeOS support for cannonlake_rvp platform.

Change-Id: Ia02407da8ab4aac2c2c33a7796fc71aea12e2925
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-08-29 17:32:33 -07:00 committed by Aaron Durbin
parent a17e4e4423
commit e1bdc6aa16
3 changed files with 53 additions and 0 deletions
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4
src/mainboard/intel/cannonlake_rvp/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_CANNONLAKE
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
config MAINBOARD_DIR
@ -55,4 +56,7 @@ config DIMM_SPD_SIZE
int
default 512
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
endif

6
src/mainboard/intel/cannonlake_rvp/Makefile.inc
View File

@ -19,6 +19,12 @@ subdirs-y += spd
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

43
src/mainboard/intel/cannonlake_rvp/chromeos.fmd Normal file
View File

@ -0,0 +1,43 @@
FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x300000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x2ff000
}
SI_BIOS@0x300000 0xd00000 {
RW_SECTION_A@0x0 0x368000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x357fc0
RW_FWID_A@0x367fc0 0x40
}
RW_SECTION_B@0x368000 0x368000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x357fc0
RW_FWID_B@0x367fc0 0x40
}
RW_MISC@0x6d0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x700000 0x200000
WP_RO@0x900000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x300000
}
}
}
}