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pcengines/apu1: Add RS485 configuration 

In RS485 mode RTS line acts as a transceiver direction control.

The datasheet is not very clear about the polarity but register setting
here is tested to drive nRTS line high when transmitting.

Also note revision of B of the super-IO has errata and 8N1 setting does
not work properly, you would need revision C of the chip assembled to
fix this.

Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14998
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki 2015-10-13 15:01:15 +03:00
parent 78f73353a3
commit e1c36aecd8
2 changed files with 29 additions and 0 deletions
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6
src/mainboard/pcengines/apu1/Kconfig
View File

@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C
endchoice
config UART_C_RS485
bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C
choice
prompt "J19 pins 11-20"
default APU1_PINMUX_OFF_D
@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D
endchoice
config UART_D_RS485
bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
endif # BOARD_PCENGINES_APU1

23
src/mainboard/pcengines/apu1/mainboard.c
View File

@ -158,6 +158,28 @@ static void config_gpio_mux(void)
gpio->enabled = CONFIG_APU1_PINMUX_GPIO1;
}
static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
{
struct resource *res;
res = new_resource(dev, reg);
res->base = val;
res->size = 0;
res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED;
}
static void config_addon_uart(void)
{
struct device *uart;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
if (uart && uart->enabled && CONFIG_UART_C_RS485)
pnp_raw_resource(uart, 0xf2, 0x12);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
if (uart && uart->enabled && CONFIG_UART_D_RS485)
pnp_raw_resource(uart, 0xf2, 0x12);
}
/**
* TODO
* SB CIMx callback
@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
config_gpio_mux();
config_addon_uart();
/* Power off unused clock pins of GPP PCIe devices */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);