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mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface type 

Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix
logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN
SGMII as the original intention is to set the PSE TSN phy
interface as RGMII.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Lean Sheng Tan 2022-05-19 09:55:20 +02:00 committed by Felix Held
parent 100514d8c7
commit e1c385ebe1
1 changed files with 0 additions and 2 deletions
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src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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@ -102,8 +102,6 @@ chip soc/intel/elkhartlake
# TSN GBE related UPDs
register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
register "PchTsnGbeSgmiiEnable" = "1"
register "PseTsnGbeSgmiiEnable[0]" = "1"
register "PseTsnGbeSgmiiEnable[1]" = "1"
register "PseDmaOwn[0]" = "Host_Owned"
register "PseDmaOwn[1]" = "Host_Owned"