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Add proper Slot 1 CPU support code/infrastructure. 

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Keith Hui 2010-03-05 16:18:38 +00:00 committed by Uwe Hermann
parent ae22bcd6d9
commit e1ec158c0a
6 changed files with 114 additions and 0 deletions
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1
src/cpu/intel/Kconfig
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@ -8,6 +8,7 @@ source src/cpu/intel/model_106cx/Kconfig
source src/cpu/intel/bga956/Kconfig
source src/cpu/intel/ep80579/Kconfig
source src/cpu/intel/slot_2/Kconfig
source src/cpu/intel/slot_1/Kconfig
source src/cpu/intel/socket_mFCPGA478/Kconfig
source src/cpu/intel/socket_mPGA478/Kconfig
source src/cpu/intel/socket_mPGA479M/Kconfig

1
src/cpu/intel/Makefile.inc
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@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
#socket_mPGA604_533Mhz
#socket_mPGA604_800Mhz

33
src/cpu/intel/slot_1/Kconfig Normal file
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@ -0,0 +1,33 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config CPU_INTEL_SLOT_1
bool
config DCACHE_RAM_BASE
hex
default 0xc0000
depends on CPU_INTEL_SLOT_1
config DCACHE_RAM_SIZE
hex
default 0x01000
depends on CPU_INTEL_SLOT_1

29
src/cpu/intel/slot_1/Makefile.inc Normal file
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@ -0,0 +1,29 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
obj-y += slot_1.o
subdirs-y += ../model_6xx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode

24
src/cpu/intel/slot_1/chip.h Normal file
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@ -0,0 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations cpu_intel_slot_1_ops;
struct cpu_intel_slot_1_config {
};

26
src/cpu/intel/slot_1/slot_1.c Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include "chip.h"
struct chip_operations cpu_intel_slot_1_ops = {
CHIP_NAME("Slot 1 CPU")
};