lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O reads
Requesting low power acpi cpu c-states has two software interfaces: Using P_LVLx I/O reads or using equivalent MWAIT requests. This change makes it more consistent with newer targets that use MWAIT requests. There also exists extended intel acpi c-states which can be enabled in two ways: - using a substate hint to the mwait request (defined in bios); - setting a model specific register (msr) Currently this is done by setting the right msr bits but with this change one can experiment by adding substate hints. Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14801 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -38,10 +38,37 @@
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#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
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#define MWAIT_RES(state, sub_state) \
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{ \
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.space_id = ACPI_ADDRESS_SPACE_FIXED, \
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
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{ \
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.resv = 0, \
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}, \
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.addrl = (((state) << 4) | (sub_state)), \
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.addrh = 0, \
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}
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static acpi_cstate_t cst_entries[] = {
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{ 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
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{ 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
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{ 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
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{
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.ctype = 1,
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.latency = 1,
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.power = 1000,
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.resource = MWAIT_RES(0, 0),
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},
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{
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.ctype = 2,
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.latency = 1,
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.power = 500,
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.resource = MWAIT_RES(1, 0),
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},
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{
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.ctype = 3,
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.latency = 17,
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.power = 250,
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.resource = MWAIT_RES(2, 0),
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},
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};
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int get_cst_entries(acpi_cstate_t **entries)
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