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mb/intel/adlrvp: Enable eMMC device for ADL-N RVP 

Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.

Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Krishna Prasad Bhat 2022-01-16 23:19:52 +05:30 committed by Felix Held
parent 7e76883f35
commit e1ff978c9a
2 changed files with 31 additions and 0 deletions
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4
src/mainboard/intel/adlrvp/devicetree_n.cb
View File

@ -16,6 +16,9 @@ chip soc/intel/alderlake
# Sagv Configuration # Sagv Configuration
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
# eMMC HS400
register "emmc_enable_hs400_mode" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector
@ -276,6 +279,7 @@ chip soc/intel/alderlake
device ref uart0 on end device ref uart0 on end
device ref gspi0 on end device ref gspi0 on end
device ref p2sb on end device ref p2sb on end
device ref emmc on end
device ref hda on device ref hda on
chip drivers/intel/soundwire chip drivers/intel/soundwire
device generic 0 on device generic 0 on

27
src/mainboard/intel/adlrvp/gpio_n.c
View File

@ -42,6 +42,33 @@ static const struct pad_config gpio_table[] = {
/* M2_SSD_DEVSLP */ /* M2_SSD_DEVSLP */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
/* I5 : NC */
PAD_NC(GPP_I5, NONE),
/* I7 : EMMC_CMD ==> EMMC_CMD */
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
/* I8 : EMMC_DATA0 ==> EMMC_D0 */
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
/* I9 : EMMC_DATA1 ==> EMMC_D1 */
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
/* I10 : EMMC_DATA2 ==> EMMC_D2 */
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
/* I11 : EMMC_DATA3 ==> EMMC_D3 */
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
/* I12 : EMMC_DATA4 ==> EMMC_D4 */
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
/* I13 : EMMC_DATA5 ==> EMMC_D5 */
PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
/* I14 : EMMC_DATA6 ==> EMMC_D6 */
PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
/* I15 : EMMC_DATA7 ==> EMMC_D7 */
PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
/* I16 : EMMC_RCLK ==> EMMC_RCLK */
PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
/* I17 : EMMC_CLK ==> EMMC_CLK */
PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
/* I18 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
/* TYPEA_CONN23_USB2_P8_OC1_N */ /* TYPEA_CONN23_USB2_P8_OC1_N */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* CRD1_PWREN */ /* CRD1_PWREN */