nb/intel/haswell: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I1d3a32a9386c0dee65eea6f9d0a2520d5e800db1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43690 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
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@ -30,66 +30,7 @@
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define GGC 0x50 /* GMCH Graphics Control */
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#define GGC_DISABLE_VGA_IO_DECODE (1 << 1)
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#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3)
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#define GGC_GTT_0MB (0 << 8)
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#define GGC_GTT_1MB (1 << 8)
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#define GGC_GTT_2MB (2 << 8)
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_D3EN (1 << 5)
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#define DEVEN_D2EN (1 << 4)
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#define DEVEN_D1F0EN (1 << 3)
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#define DEVEN_D1F1EN (1 << 2)
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#define DEVEN_D1F2EN (1 << 1)
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#define DEVEN_D0EN (1 << 0)
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define MESEG_BASE 0x70 /* Management Engine Base */
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#define MESEG_LIMIT 0x78 /* Management Engine Limit */
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#define REMAPBASE 0x90 /* Remap base */
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#define REMAPLIMIT 0x98 /* Remap limit */
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#define TOM 0xa0 /* Top of DRAM in memory controller space */
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define BDSM 0xb0 /* Base Data Stolen Memory */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define SKPAD 0xdc /* Scratchpad Data */
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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#define SPCAPCTRL (1 << 25)
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#define L3HIT2PEND_DIS (1 << 20)
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#define PRSCAPDIS (1 << 2)
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#define GLBIOTLBINV (1 << 1)
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#define GLBCTXTINV (1 << 0)
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#include "hostbridge_regs.h"
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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@ -116,6 +57,14 @@
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/* As there are many registers, define them on a separate file */
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#include "mchbar_regs.h"
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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#define SPCAPCTRL (1 << 25)
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#define L3HIT2PEND_DIS (1 << 20)
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#define PRSCAPDIS (1 << 2)
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#define GLBIOTLBINV (1 << 1)
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#define GLBCTXTINV (1 << 0)
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __HASWELL_HOSTBRIDGE_REGS_H__
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#define __HASWELL_HOSTBRIDGE_REGS_H__
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define GGC 0x50 /* GMCH Graphics Control */
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#define GGC_DISABLE_VGA_IO_DECODE (1 << 1)
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#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3)
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#define GGC_GTT_0MB (0 << 8)
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#define GGC_GTT_1MB (1 << 8)
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#define GGC_GTT_2MB (2 << 8)
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_D3EN (1 << 5)
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#define DEVEN_D2EN (1 << 4)
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#define DEVEN_D1F0EN (1 << 3)
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#define DEVEN_D1F1EN (1 << 2)
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#define DEVEN_D1F2EN (1 << 1)
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#define DEVEN_D0EN (1 << 0)
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define MESEG_BASE 0x70 /* Management Engine Base */
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#define MESEG_LIMIT 0x78 /* Management Engine Limit */
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#define REMAPBASE 0x90 /* Remap base */
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#define REMAPLIMIT 0x98 /* Remap limit */
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#define TOM 0xa0 /* Top of DRAM in memory controller space */
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define BDSM 0xb0 /* Base Data Stolen Memory */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define SKPAD 0xdc /* Scratchpad Data */
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */
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