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ec: Reserve correct ioport regions for Chrome OS EC to use 

The LPC-based ChromeOS EC uses several ioport regions to communicate with
the AP. In order for the new unified userspace access method to work, we
need them to be reserved by the BIOS.

Before /proc/ioports shows:

  0800-0803
  0804-08ff

We'd like just a single 256-byte region at 0x800, but ASL can't handle that.
So this will work:

  0800-087f
  0880-08ff

Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: http://review.coreboot.org/3746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Bill Richardson 2013-06-12 10:50:41 -07:00 committed by Stefan Reinauer
parent a86c33a31a
commit e221aad27f
2 changed files with 52 additions and 16 deletions
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17
src/ec/google/chromeec/acpi/superio.asl
View File

@ -29,8 +29,9 @@
* SIO_EC_HOST_ENABLE : Enable EC host command interface resources * SIO_EC_HOST_ENABLE : Enable EC host command interface resources
* EC_LPC_ADDR_HOST_DATA : EC host command interface data port * EC_LPC_ADDR_HOST_DATA : EC host command interface data port
* EC_LPC_ADDR_HOST_CMD : EC host command interface command port * EC_LPC_ADDR_HOST_CMD : EC host command interface command port
* EC_LPC_ADDR_HOST_ARGS : EC host command arguments * EC_HOST_CMD_REGION0 : EC host command buffer
* EC_LPC_ADDR_HOST_PARAM : EC host command parameter buffer * EC_HOST_CMD_REGION1 : EC host command buffer
* EC_HOST_CMD_REGION_SIZE : EC host command buffer size
*/ */
// Scope is \_SB.PCI0.LPCB // Scope is \_SB.PCI0.LPCB
@ -75,9 +76,8 @@ Device (SIO) {
{ {
FixedIO (EC_LPC_ADDR_HOST_DATA, 1) FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
FixedIO (EC_LPC_ADDR_HOST_CMD, 1) FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
FixedIO (EC_LPC_ADDR_HOST_ARGS, 4) FixedIO (EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION_SIZE)
FixedIO (EC_LPC_ADDR_HOST_PARAM, FixedIO (EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION_SIZE)
EC_HOST_PARAM_SIZE)
}) })
Name (_PRS, ResourceTemplate () Name (_PRS, ResourceTemplate ()
@ -85,9 +85,10 @@ Device (SIO) {
StartDependentFn (0, 0) { StartDependentFn (0, 0) {
FixedIO (EC_LPC_ADDR_HOST_DATA, 1) FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
FixedIO (EC_LPC_ADDR_HOST_CMD, 1) FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
FixedIO (EC_LPC_ADDR_HOST_ARGS, 4) FixedIO (EC_HOST_CMD_REGION0,
FixedIO (EC_LPC_ADDR_HOST_PARAM, EC_HOST_CMD_REGION_SIZE)
EC_HOST_PARAM_SIZE) FixedIO (EC_HOST_CMD_REGION1,
EC_HOST_CMD_REGION_SIZE)
} }
EndDependentFn () EndDependentFn ()
}) })

51
src/ec/google/chromeec/ec_commands.h
View File

@ -42,10 +42,16 @@
#define EC_LPC_ADDR_HOST_CMD 0x204 #define EC_LPC_ADDR_HOST_CMD 0x204
/* I/O addresses for host command args and params */ /* I/O addresses for host command args and params */
#define EC_LPC_ADDR_HOST_ARGS 0x800 #define EC_LPC_ADDR_HOST_ARGS 0x800 /* and 0x801, 0x802, 0x803 */
#define EC_LPC_ADDR_HOST_PARAM 0x804 #define EC_LPC_ADDR_HOST_PARAM 0x804
#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ #define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
* and they tell the kernel that so we have to think of it as two parts. */
#define EC_HOST_CMD_REGION0 0x800
#define EC_HOST_CMD_REGION1 0x880
#define EC_HOST_CMD_REGION_SIZE 0x80
/* EC command register bit functions */ /* EC command register bit functions */
#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ #define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ #define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
@ -726,15 +732,44 @@ enum lightbar_command {
/*****************************************************************************/ /*****************************************************************************/
/* LED control commands */ /* LED control commands */
#define EC_CMD_LED_SET 0x29 #define EC_CMD_LED_CONTROL 0x29
#define EC_LED_FLAGS_AUTO (1 << 1) enum ec_led_id {
EC_LED_ID_BATTERY_LED = 0,
EC_LED_ID_POWER_BUTTON_LED,
EC_LED_ID_ADAPTER_LED,
};
struct ec_params_led_set { /* LED control flags */
uint8_t r; #define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
uint8_t g; #define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */
uint8_t b; /* Used as yellow if there is no blue LED */
uint8_t flags; enum ec_led_colors {
EC_LED_COLOR_RED = 0,
EC_LED_COLOR_GREEN,
EC_LED_COLOR_BLUE,
EC_LED_COLOR_YELLOW,
EC_LED_COLOR_WHITE,
EC_LED_COLOR_COUNT
};
struct ec_params_led_control {
uint8_t led_id; /* Which LED to control */
uint8_t flags; /* Control flags */
uint8_t brightness[EC_LED_COLOR_COUNT];
} __packed;
struct ec_response_led_control {
/*
* Available brightness value range.
*
* Range 0 means color channel not present.
* Range 1 means on/off control.
* Other values means the LED is control by PWM.
*/
uint8_t brightness_range[EC_LED_COLOR_COUNT];
} __packed; } __packed;
/*****************************************************************************/ /*****************************************************************************/