drivers/gma: remove unused code
We had brought this code in from the kernel but found it best to use mainboard- or chipset specific versions. Firmware should strive to be as non-generic as possible. Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172625 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Ronald G. Minnich
Isaac Christensen
parent
e00ba2168b
commit
e231de2134
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@ -180,14 +180,10 @@ struct intel_dp {
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/* we may yet need these. */
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void intel_dp_mode_set(struct intel_dp *intel_dp);
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
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void intel_dp_complete_link_train(struct intel_dp *intel_dp);
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void intel_dp_link_down(struct intel_dp *intel_dp);
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int intel_dp_i2c_init(struct intel_dp *intel_dp);
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int intel_dp_i2c_aux_ch(struct intel_dp *intel_dp,
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int mode, uint8_t write_byte, uint8_t *read_byte);
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void
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intel_dp_dpms(struct intel_dp *intel_dp, int mode);
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int intel_dp_get_dpcd(struct intel_dp *intel_dp);
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struct edid *intel_dp_get_edid(struct intel_dp *intel_dp);
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@ -205,7 +201,10 @@ int intel_dp_aux_ch(struct intel_dp *intel_dp,
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uint8_t *send, int send_bytes,
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uint8_t *recv, int recv_size);
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void unpack_aux(u32 src, uint8_t *dst, int dst_bytes);
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int intel_channel_eq_ok(struct intel_dp *intel_dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE]);
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void ironlake_edp_panel_off(struct intel_dp *intel_dp);
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void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
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/* drm_dp_helper.c */
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int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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@ -821,7 +821,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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}
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}
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static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
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void ironlake_edp_panel_off(struct intel_dp *intel_dp)
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{
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u32 pp;
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@ -863,7 +863,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
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////POSTING_READ(PCH_PP_CONTROL);
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}
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static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
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void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
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{
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u32 pp;
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@ -930,75 +930,6 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
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}
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}
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}
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// not sure if needed yet or not.
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void intel_dp_prepare(struct intel_dp *intel_dp);
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void intel_dp_prepare(struct intel_dp *intel_dp)
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{
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ironlake_edp_backlight_off(intel_dp);
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ironlake_edp_panel_off(intel_dp);
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/* Wake up the sink first */
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ironlake_edp_panel_vdd_on(intel_dp);
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intel_dp_sink_dpms(intel_dp, 0);
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intel_dp_link_down(intel_dp);
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ironlake_edp_panel_vdd_off(intel_dp, 0);
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/* Make sure the panel is off before trying to
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* change the mode
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*/
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}
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// might be useful.
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void intel_dp_commit(struct intel_dp *intel_dp);
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void intel_dp_commit(struct intel_dp *intel_dp)
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{
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ironlake_edp_panel_vdd_on(intel_dp);
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intel_dp_sink_dpms(intel_dp, 0);
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intel_dp_start_link_train(intel_dp);
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ironlake_edp_panel_on(intel_dp);
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ironlake_edp_panel_vdd_off(intel_dp, 1);
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intel_dp_complete_link_train(intel_dp);
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ironlake_edp_backlight_on(intel_dp);
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intel_dp->dpms_mode = 0;
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}
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void
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intel_dp_dpms(struct intel_dp *intel_dp, int mode)
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{
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uint32_t dp_reg = gtt_read(intel_dp->output_reg);
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printk(BIOS_SPEW, "%s: power %s\n", __func__, mode ? "off" : "on");
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if (mode){
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ironlake_edp_backlight_off(intel_dp);
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ironlake_edp_panel_off(intel_dp);
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ironlake_edp_panel_vdd_on(intel_dp);
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intel_dp_sink_dpms(intel_dp, mode);
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intel_dp_link_down(intel_dp);
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ironlake_edp_panel_vdd_off(intel_dp, 0);
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if (is_cpu_edp(intel_dp))
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ironlake_edp_pll_off();
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} else {
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if (is_cpu_edp(intel_dp))
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ironlake_edp_pll_on();
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ironlake_edp_panel_vdd_on(intel_dp);
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intel_dp_sink_dpms(intel_dp, mode);
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if (!(dp_reg & DP_PORT_EN)) {
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intel_dp_start_link_train(intel_dp);
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ironlake_edp_panel_on(intel_dp);
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ironlake_edp_panel_vdd_off(intel_dp, 1);
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intel_dp_complete_link_train(intel_dp);
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} else
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ironlake_edp_panel_vdd_off(intel_dp, 0);
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ironlake_edp_backlight_on(intel_dp);
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}
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intel_dp->dpms_mode = mode;
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}
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/*
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* Native read with retry for link status and receiver capability reads for
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@ -1055,31 +986,6 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
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return link_status[r - DP_LANE0_1_STATUS];
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}
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#if 0
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static uint8_t
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intel_get_adjust_request_voltage(uint8_t adjust_request[2],
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int lane)
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{
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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uint8_t l = adjust_request[lane>>1];
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return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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static uint8_t
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intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
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int lane)
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{
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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uint8_t l = adjust_request[lane>>1];
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return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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#endif
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const char *voltage_names[] = {
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"0.4V", "0.6V", "0.8V", "1.2V"
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};
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@ -1356,7 +1262,7 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE],
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#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE| \
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DP_LANE_CHANNEL_EQ_DONE| \
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DP_LANE_SYMBOL_LOCKED)
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static int
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int
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intel_channel_eq_ok(struct intel_dp *intel_dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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@ -1609,134 +1515,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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intel_dp->DP = DP;
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}
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void
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intel_dp_complete_link_train(struct intel_dp *intel_dp)
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{
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int channel_eq = 0;
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int tries, cr_tries;
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uint32_t DP = intel_dp->DP;
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/* channel equalization */
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tries = 0;
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cr_tries = 0;
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channel_eq = 0;
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for (;;) {
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/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
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uint32_t signal_levels;
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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if (cr_tries > 5) {
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printk(BIOS_ERR, "failed to train DP, aborting\n");
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intel_dp_link_down(intel_dp);
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break;
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}
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if (intel_dp->is_haswell) {
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signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
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DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
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printk(BIOS_SPEW, "%s: new DP %08x\n", __func__,
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DP);
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} else if ((intel_dp->gen == 7) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
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} else if ((intel_dp->gen == 6) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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/* channel eq pattern */
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if (!intel_dp_set_link_train(intel_dp, DP,
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DP_TRAINING_PATTERN_2 |
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DP_LINK_SCRAMBLING_DISABLE))
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break;
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udelay(40000); /* was 400 */
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if (!intel_dp_get_link_status(intel_dp, link_status))
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break;
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/* Make sure clock is still ok */
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if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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printk(BIOS_SPEW, "%s: Clock recovery is NOT ok"
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": restarting from the start\n", __func__);
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intel_dp_start_link_train(intel_dp);
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cr_tries++;
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continue;
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}
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if (intel_channel_eq_ok(intel_dp, link_status)) {
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printk(BIOS_SPEW, "%s: success\n", __func__);
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channel_eq = 1;
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break;
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}
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/* Try 5 times, then try clock recovery if that fails */
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if (tries > 5) {
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printk(BIOS_SPEW, "%s: tries > 5,recovering.\n",
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__func__);
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intel_dp_link_down(intel_dp);
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intel_dp_start_link_train(intel_dp);
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tries = 0;
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cr_tries++;
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continue;
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}
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/* Compute new intel_dp->train_set as requested by target */
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printk(BIOS_SPEW, "%s: adjust the train\n", __func__);
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intel_get_adjust_train(intel_dp, link_status);
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++tries;
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}
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//gtt_write(intel_dp->output_reg,reg);
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////POSTING_READ(intel_dp->output_reg);
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intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
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}
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void
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intel_dp_link_down(struct intel_dp *intel_dp)
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{
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uint32_t DP = intel_dp->DP;
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if ((gtt_read(intel_dp->output_reg) & DP_PORT_EN) == 0)
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return;
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if (intel_dp->is_haswell){
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printk(BIOS_SPEW, "%s: It's a haswell, skip this\n", __func__);
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return;
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}
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if (is_edp(intel_dp)) {
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DP &= ~DP_PLL_ENABLE;
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gtt_write(intel_dp->output_reg,DP);
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////POSTING_READ(intel_dp->output_reg);
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udelay(100);
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}
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if (intel_dp->has_pch_cpt && ((intel_dp->gen == 7) || !is_cpu_edp(intel_dp))) {
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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gtt_write(intel_dp->output_reg,DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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} else {
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DP &= ~DP_LINK_TRAIN_MASK;
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gtt_write(intel_dp->output_reg,DP | DP_LINK_TRAIN_PAT_IDLE);
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}
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////POSTING_READ(intel_dp->output_reg);
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mdelay(17);
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if (is_edp(intel_dp)) {
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if (intel_dp->has_pch_cpt && ((intel_dp->gen == 7) || !is_cpu_edp(intel_dp)))
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DP |= DP_LINK_TRAIN_OFF_CPT;
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else
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DP |= DP_LINK_TRAIN_OFF;
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}
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DP &= ~DP_AUDIO_OUTPUT_ENABLE;
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gtt_write(intel_dp->output_reg,DP & ~DP_PORT_EN);
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////POSTING_READ(intel_dp->output_reg);
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mdelay(600000); //intel_dp->panel_power_down_delay);
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}
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int
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intel_dp_get_dpcd(struct intel_dp *intel_dp)
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{
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