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soc/amd/mendocino/acpi: rework C state info table handling 

Rework the way the C state info is generated before it gets passed to
acpigen_write_CST_package in generate_cpu_entries by separating the data
from the code. For this, the newly introduced common get_cstate_info
function is used. Separating the data from the code will eventually
allow moving generate_cpu_entries to the common AMD code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3669c66094f0137081888ebdd1af838e2ea269b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-03-07 00:03:46 +01:00
parent ceafcae078
commit e23c42577e
2 changed files with 29 additions and 45 deletions
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1
src/soc/amd/mendocino/Kconfig
View File

@ -36,6 +36,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
select SOC_AMD_COMMON_BLOCK_AOAC

73
src/soc/amd/mendocino/acpi.c
View File

@ -225,15 +225,38 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
return pstate_count;
}
const acpi_cstate_t cstate_cfg_table[] = {
[0] = {
.ctype = 1,
.latency = 1,
.power = 0,
},
[1] = {
.ctype = 2,
.latency = 0x12,
.power = 0,
},
[2] = {
.ctype = 3,
.latency = 350,
.power = 0,
},
};
const acpi_cstate_t *get_cstate_config_data(size_t *size)
{
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t pstate_count, cpu;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
uint32_t cstate_base_address =
rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
@ -246,48 +269,8 @@ void generate_cpu_entries(const struct device *device)
.addrl = PS_STS_REG,
};
const acpi_cstate_t cstate_info[] = {
[0] = {
.ctype = 1,
.latency = 1,
.power = 0,
.resource = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 2,
.bit_offset = 2,
.addrl = 0,
.addrh = 0,
},
},
[1] = {
.ctype = 2,
.latency = 0x12,
.power = 0,
.resource = {
.space_id = ACPI_ADDRESS_SPACE_IO,
.bit_width = 8,
.bit_offset = 0,
.addrl = cstate_base_address + 1,
.addrh = 0,
.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
},
},
[2] = {
.ctype = 3,
.latency = 350,
.power = 0,
.resource = {
.space_id = ACPI_ADDRESS_SPACE_IO,
.bit_width = 8,
.bit_offset = 0,
.addrl = cstate_base_address + 2,
.addrh = 0,
.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
},
},
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
@ -308,7 +291,7 @@ void generate_cpu_entries(const struct device *device)
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info));
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);