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rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed 

This patch doubles the ACLK peripheral clock for the PD_BUS power domain
to 297MHz, which is the closest to the maximum of 300MHz we can reach by
dividing GPLL. This frequency directly translates into SRAM speed, so
maximizing it has a huge impact on boot speed (especially with the lack
of SRAM caching).

BUG=chrome-os-partner:32987
TEST=Booted Veyron_Pinky. Hacked timestamps into vboot and confirmed
that the (visibly) long signature verification times are nearly halved.

Change-Id: Iafa3044854a4058a7f885c775119d964a6295de4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c230585f4344d0eab4f8eeaa761869965f2da08a
Original-Change-Id: I3f19eaa3d97dcc6235d820c71eb5edf2ae87d647
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224524
Original-Trybot-Ready: Doug Anderson <dianders@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9600
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner 2014-10-20 18:04:29 -07:00 committed by Patrick Georgi
parent 4913cb78d2
commit e244986e40
1 changed files with 2 additions and 1 deletions
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3
src/soc/rockchip/rk3288/include/soc/clock.h
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@ -29,7 +29,8 @@
#define CPLL_HZ (384*MHz) #define CPLL_HZ (384*MHz)
#define NPLL_HZ (384*MHz) #define NPLL_HZ (384*MHz)
#define PD_BUS_ACLK_HZ (148500*KHz) /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */
#define PD_BUS_ACLK_HZ (297000*KHz)
#define PD_BUS_HCLK_HZ (148500*KHz) #define PD_BUS_HCLK_HZ (148500*KHz)
#define PD_BUS_PCLK_HZ (74250*KHz) #define PD_BUS_PCLK_HZ (74250*KHz)