From e24f97c081f3e134362081913793d5adb90eddd5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 2 Apr 2021 22:42:53 +0200 Subject: [PATCH] nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t410/devicetree.cb | 2 -- src/mainboard/lenovo/x201/devicetree.cb | 2 -- .../packardbell/ms2290/devicetree.cb | 2 -- src/northbridge/intel/ironlake/chip.h | 5 ----- src/northbridge/intel/ironlake/raminit.c | 19 +------------------ 5 files changed, 1 insertion(+), 29 deletions(-) diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index af770dc01c..5f167df4b8 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -23,8 +23,6 @@ chip northbridge/intel/ironlake end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543dee3..e142a1c692 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ chip northbridge/intel/ironlake end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b57b3feba8..d5f96cba6e 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -24,8 +24,6 @@ chip northbridge/intel/ironlake end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bced5..ab589ea221 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ struct northbridge_intel_ironlake_config { u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073ddae89..34e56571ca 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ static void program_board_delay(struct raminfo *info) } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ static void program_total_memory_map(struct raminfo *info) uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096)